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Full support for attributes in Yosys #27

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8 of 12 tasks
mkurc-ant opened this issue May 28, 2019 · 5 comments
Open
8 of 12 tasks

Full support for attributes in Yosys #27

mkurc-ant opened this issue May 28, 2019 · 5 comments

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@mkurc-ant
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mkurc-ant commented May 28, 2019

Support for attributes on parameters was successfully landed (#25). However, there are several cases of attribute usage still not supported by the Yosys which might be useful in Symbiflow:

(not a complete list)

  • Module declaration: (* optimize *) module control ( ... );
  • Port declaration (input/output/inout): (* port_attr *) input clk;
  • Parameter: (* param_attr *) parameter WIDTH = 10;
  • Local parameter: (* localparam_attr *) localparam MAGIC = 8'hFE;
  • Net/Variable (wire/reg): (* state_variable *) reg [7:0] S;
  • Port connection: dff il (q, d, (* clock_line *) ckl, rst);
  • Suffix to an operator: sum = a + (* ripple_adder *) b;
  • Suffix to a function call: assign next_state = fsm_func(* meally_fsm *) (state, a, b, c);
  • Module instantiation: (* inst_attr *) my_module my_instance (...);
  • Generate statement: (* gen_attr *) generate ...
  • On specify block: (* spec_attr *) specify ...
  • On specparam declaration: (* specparam_attr *) specparam T = 10.0; ...
@mkurc-ant
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@mithro I created this issue to keep track of attribute related features we want in Yosys. Those examples are just a subset of all possible attribute placement cases.

Anyway, can you give an real world example of usage of an attribute on a port connection ?

@mithro
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mithro commented May 29, 2019

This is how I wanted to use the attribute on a port connection;

	MUX2 rmux (
		(* pack = "LUT5toLUT6; LUT5toLUT7; LUT5toLUT8" *)
		.I0(n5lut_0_out),
		(* pack = "LUT5x2" *)
		.I1(n5lut_1_out),
		.O(f6mux_O)
	);

@mkurc-ant
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I started to work on attributes on port connections. And I encountered a problem - it seems that at some point Yosys swaps what RTLIL::SigSpec object refers to but not its attributes (which I added).

@mithro
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mithro commented May 31, 2019

These examples are from Verilog — 2001 - A Guide to the New Features of the Verilog® Hardware Description Language Section 25. Attributes,

always @(state) //state machine with one-hot encoding
  (* full_case, parallel_case *) case (state)
  3'b001: next_state = 3'b010;
  3'b010: next_state = 3'b100;
  3'b100: next_state = 3'b001;
endcase 

The attribute is specified as a prefix to a declaration, a module item, a statement or
a port connection. Three examples are:

(* optimize *) module control ( ... );

(* state_variable *) reg [7:0] S;

dff il (q, d, (* clock_line *) ckl, rst};

The attribute is specified as a suffix to an operator or the function name in a function call.

sum = a + (* ripple_adder *) b;

assign next_state = fsm_func(* meally_fsm *) (state, a, b, c); 

@mkurc-ant
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@mithro It's working: #30

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