How is the D set and Q used from a register?

[bbqbob]

I am new to SystemRDL and I am struggling with what I think should be a very simple thing. I want to create two registers, each with only 1 bit. Register 1 is a status register that tells me the present value of a wire that originates from outside of the block. Register 2 is a control register that set and holds the value of a different wire. That wire would be used outside of the block. Defining the registers was straight-forward, but I am struggling with how to attach the input and output wires to the registers, especially the output.

Here is what I have:

addrmap example {
    name = "One control, one status";
    desc = "One status register with 1 bit reflecting a input signal value.  
	        One control register with 1 bit whose value drives a signal value.";

	// block has 1 input signal and 1 output signal
	signal { signalwidth=1; } inputs;
	signal { signalwidth=1; } outputs;
	
	// two registers: 1 status and 1 control
	// a read of the status register should sample the input signal and return the present value of that wire
	reg status {
		name = "status_reg";
		field stat_bit {
			name = "stat_bit";
			// wire that continually assigns value
			hw = w;
			sw = r;
			signal input_sig {
				name="input_status_signal";
				async; 
			} input_signal;
			next = input_signal;
		} sbit_1;
	} reg_stat;

	// the register value should continually drive the output signal
	reg control {
		name = "control_reg";
		field ctl_bit {
			name = "control bit";
			// storage element that continually drives the wire
			hw = r;
			sw = rw;
                        // the spec isn't clear, but it seems acceptable to have signals defined here, but what is is attached to?
			signal output_sig {
				name = "output_control_signal";
			} output_signal;
		} cbit_1;
		// want to tie the signal to the Q of the register field FF, but this doesn't work
		//cbit_1.output_signal = cbit_1;
	} reg_control;
	
	// the following compiles, but looks like sbit_1 is set twice (here and from input_signal)
	reg_stat.sbit_1->next = inputs;
	
	// the following make more sense, but don't compile
	// reg_stat.sbit_1.input_signal = inputs;
	//  reg_stat->sbit_1->input_signal = inputs;
	
	// want the wire output to be the Q of the FF
	// think the module signal should be set to the reg field signal
	// desire outputs->value = reg_control.cbit_1.output_signal;
	// outputs = reg_control->cbit_1; 
	// outputs = reg_control.cbit_1;
};

How do I assign the block level signal to the register field level signal to set value that is read?
How do I assign the Q output of the control register to the output wire of the block?

Thanks in advance for any help.

[amykyta3]

Hi and thanks for taking an interest in SystemRDL!

You're actually quite close already. As you learn more about the language, you'll see that SystemRDL does a lot of things through inference. The hw property implicitly controls what the "hardware-facing" interface looks like. Setting hw = r implicitly infers an output signal from the block, since the hardware-side "reads" the value of the register. Similarly, hw = w infers an input signal that the outside logic "writes" to the register.
So for your example, all you need is the following:

addrmap example {
    name = "One control, one status";
    desc = "One status register with 1 bit reflecting a input signal value.  
            One control register with 1 bit whose value drives a signal value.";
    
    // two registers: 1 status and 1 control
    // a read of the status register should sample the input signal and return the present value of that wire
    reg status {
        name = "status_reg";
        field stat_bit {
            name = "stat_bit";
            // wire that continually assigns value
            hw = w;
            sw = r;
        } sbit_1;
    } reg_stat;

    // the register value should continually drive the output signal
    reg control {
        name = "control_reg";
        field ctl_bit {
            name = "control bit";
            // storage element that continually drives the wire
            hw = r;
            sw = rw;
        } cbit_1;
    } reg_control;
};

The SystemRDL spec has a really good table in section 9 that shows some combinations and what they end up inferring:

From there, you can use the numerous other properties to further augment the implied behavior.
If you're using the PeakRDL-regblock SystemVerilog generator, I have some documentation some of these extra properties are implemented in that code generator: https://peakrdl-regblock.readthedocs.io/en/latest/props/field.html

The extra signal components you had are not necessary since everything you wanted is already implied. Signal components are actually pretty rarely used. They can be useful if you want to define some auxiliary inputs to control some special behavior.

[bbqbob]

Thank you for the help. I had incorrectly assumed that signals were an essential part of the description; I didn't realize that things were inferred as part of language, so your response put me back on the right track.