SystemRDL missing addressing modes

[RasmusGOlsen]

I'm a little confused that the SystemRDL standard only allows byte mapped addressing modes. I'm working on a project where each address is assigned based on the logical register itself and not based on the register size. This kind of disqualifies SystemRDL since this addressing mode is not supported. I'm thinking about submitting a suggestion to accellera.org for additional addressing modes. Is there anyone here that is in a similar situation?

[pdonahue-ventana]

I'm also annoyed by this. We just shift the address. So if you have 32b registers at addresses 0,1,2,3 then you can have the RDL specify addresses 0,4,8,12 and use {address,2'b00} as the address in RDL.

[RasmusGOlsen]

In my case, this is not possible since we allow an arbitrary size of registers, even wider than the width of the data bus. Also, we use multiple address spaces with different addressing modes. I added a user-defined property and patched the compiler. Not ideal, but that was the only option I could come up with.

[udif]

In my case, this is not possible since we allow an arbitrary size of registers, even wider than the width of the data bus. Also, we use multiple address spaces with different addressing modes. I added a user-defined property and patched the compiler. Not ideal, but that was the only option I could come up with.

I looked at your forks but couldn't find your specific changes relating to non byte-addressable address spaces. Is it part of your github SystemRDL repo forks?

[RasmusGOlsen]

No, unfortunately, it's not. I did this for the company I worked for at that time. I also made the change without changing the source code of the compiler by "monkey patching" the register size function so that the function always returns the size of 1 byte, when in that address mode.

[udif]

Thanks anyway!

[udif]

I think I'll try adding this myself by adding a new addrmap property (addrwordsize) that would set the address bus units in bytes or bits (TBD).
My intention is to convert everything to byte addresses internally early in the parsing stages, and convert back to my units within each export plugin I use (it seems safer than changing the internal logic from bytes to some other unit). I could add a test that makes sure all components are generated with the proper minimal alignment of the wordsize.

[amykyta3]

Until Accellera defines something otherwise, addresses in RDL will always be interpreted as byte addresses. I'm not interested in breaking away from the standard for this project (because then whats the point of a standardized language?)

Using a User Defined Property is a good way to extend the language to describe additional node attributes. See this page for how they work with the compiler: https://systemrdl-compiler.readthedocs.io/en/stable/api/udp.html

[udif]

The main objective here is to be able to input and output non-byte addresses. (I'm pushing for replacing an Excel-based homegrown system that uses word addressing schemes on different ports, based on the port's width - register allocation can always increment by 1 if needed).

Output can be easily handled by adding a UDP at the addrmap level and handling it by the various exporters.
I was willing to break the standard, and maintaining a separate branch, since inputting word addresses was the critical part for me. As the working group is now dormant, I don't expect any new releases soon, if ever.

However, you gave me an idea - I can use a verilog `define macro with an argument to handle address translation on the input side. It will be less pretty, but functional.
Given that the effort needed to do this is minimal compared to my original plan, I'll probably drop any effort to extend the parser.

[amykyta3]

Yeah agree. A simple `define macro is definitely the easiest way to go, is pretty lightweight in terms of syntax, and you get the bonus of not breaking from the standard. It may not matter for you today, but you never know where your future usage may take you.