{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":113055122,"defaultBranch":"master","name":"cryptogams","ownerLogin":"dot-asm","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2017-12-04T14:46:59.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/9038069?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1515533232.0","currentOid":""},"activityList":{"items":[{"before":"d29f640e4ae40ba520dfb1afa161a56218aee9bd","after":"65daf83d8e264b9343b514c50ca27131e61e4d96","ref":"refs/heads/master","pushedAt":"2024-06-03T16:21:41.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/ctmult-riscv.pl: add CHERI support.","shortMessageHtmlLink":"riscv/ctmult-riscv.pl: add CHERI support."}},{"before":"0f73dcd7be597e93658a5bff12ddb065e462e05a","after":"d29f640e4ae40ba520dfb1afa161a56218aee9bd","ref":"refs/heads/master","pushedAt":"2024-06-03T16:18:01.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/sha512-riscv.pl: add CHERI support.","shortMessageHtmlLink":"riscv/sha512-riscv.pl: add CHERI support."}},{"before":"f96f1a44abc1ddb6b54d608cd0a4507ca69a8c6a","after":"0f73dcd7be597e93658a5bff12ddb065e462e05a","ref":"refs/heads/master","pushedAt":"2024-06-02T15:44:42.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/keccak1600-riscv.pl: add CHERI support.","shortMessageHtmlLink":"riscv/keccak1600-riscv.pl: add CHERI support."}},{"before":"b55cf2e6e100decc74113ede40460563a483e6b2","after":"f96f1a44abc1ddb6b54d608cd0a4507ca69a8c6a","ref":"refs/heads/master","pushedAt":"2024-06-02T10:32:45.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/*: add JH7110 results.","shortMessageHtmlLink":"riscv/*: add JH7110 results."}},{"before":"cd4306d7b00e183f24235483d441187eaef4646e","after":"b55cf2e6e100decc74113ede40460563a483e6b2","ref":"refs/heads/master","pushedAt":"2024-03-16T12:08:22.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"x86_64/x86_64-xlate.pl: handle .section .rodata directive.","shortMessageHtmlLink":"x86_64/x86_64-xlate.pl: handle .section .rodata directive."}},{"before":"9573617848d141998e2771409d267596667c59d4","after":"cd4306d7b00e183f24235483d441187eaef4646e","ref":"refs/heads/master","pushedAt":"2024-03-03T17:41:50.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/keccak1600-riscv.pl: rethink bit interleaving in 32-bit code path.\n\nUpon closer inspection bit interleaving is beneficial only in combination\nwith rotate instruction.","shortMessageHtmlLink":"riscv/keccak1600-riscv.pl: rethink bit interleaving in 32-bit code path."}},{"before":"1f563fafeb7bb8b35b7ff894f86e31d3745d190e","after":"9573617848d141998e2771409d267596667c59d4","ref":"refs/heads/master","pushedAt":"2024-02-19T19:45:57.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"Add sha512-riscv.pl module.","shortMessageHtmlLink":"Add sha512-riscv.pl module."}},{"before":"d4d9d3c5b0aaad0a5a56d1e6db611bfbd467cbf5","after":"1f563fafeb7bb8b35b7ff894f86e31d3745d190e","ref":"refs/heads/master","pushedAt":"2023-11-02T11:51:51.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"Add arm/vpaes-armv7.pl.","shortMessageHtmlLink":"Add arm/vpaes-armv7.pl."}},{"before":"d2850abad8e12d643b27bc391349c49bd003fbc9","after":"d4d9d3c5b0aaad0a5a56d1e6db611bfbd467cbf5","ref":"refs/heads/master","pushedAt":"2023-10-29T15:24:17.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/keccak1600-riscv.pl: use rorw even in 32-bit code path.","shortMessageHtmlLink":"riscv/keccak1600-riscv.pl: use rorw even in 32-bit code path."}},{"before":"821f04ce35f8bb88407f96beb49987a3c201cbdc","after":"d2850abad8e12d643b27bc391349c49bd003fbc9","ref":"refs/heads/master","pushedAt":"2023-10-28T09:30:28.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/chacha-riscv.pl: rethink HROUND().","shortMessageHtmlLink":"riscv/chacha-riscv.pl: rethink HROUND()."}},{"before":"cff410ef892baf2ea9803700d2c904141f303117","after":"821f04ce35f8bb88407f96beb49987a3c201cbdc","ref":"refs/heads/master","pushedAt":"2023-10-27T17:16:03.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/keccak1600-riscv.pl: add support for bit-manipulation extension.","shortMessageHtmlLink":"riscv/keccak1600-riscv.pl: add support for bit-manipulation extension."}},{"before":"ac7551667c13d9db591b1c097d40ec5ef9274ab9","after":"cff410ef892baf2ea9803700d2c904141f303117","ref":"refs/heads/master","pushedAt":"2023-10-25T20:22:18.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"riscv/chacha-riscv.pl: add a vector \"teater\" implementation.\n\n[and add C910 results.]","shortMessageHtmlLink":"riscv/chacha-riscv.pl: add a vector \"teater\" implementation."}},{"before":"9ee843739269dd87eb9b385afce99a915dddeba3","after":"ac7551667c13d9db591b1c097d40ec5ef9274ab9","ref":"refs/heads/master","pushedAt":"2023-10-15T13:53:20.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"x86_64/sha512-x86_64.pl: add support for Intel SHA512 extension.","shortMessageHtmlLink":"x86_64/sha512-x86_64.pl: add support for Intel SHA512 extension."}},{"before":"3e1328144320dd5fb23937c6582242461df0b257","after":"9ee843739269dd87eb9b385afce99a915dddeba3","ref":"refs/heads/master","pushedAt":"2023-10-08T17:25:40.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"arm/*-armv8.pl: add support for Morello, CHERI aarch64 processor.\n\nLong-input performance results are virtually indistinguishable from\nthose for Cortex-A76. [Which is why they are not explicitly listed.]\nShort-input performance is naturally lower and appears to be affected\nmostly by the additional instructions compiler issues to adjust the\n\"capabilities,\" the 'C' in 'CHERI'. The overhead varies depending on\nthe algorithm and how the benchmark loop is organized, one can note\nmarginal difference, 20%, 40%, ...","shortMessageHtmlLink":"arm/*-armv8.pl: add support for Morello, CHERI aarch64 processor."}},{"before":"d5f40a698b9087808399166cf7cdbe46ed493cc5","after":"3e1328144320dd5fb23937c6582242461df0b257","ref":"refs/heads/master","pushedAt":"2023-06-30T16:30:46.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"arm/arm-xlate.pl: handle .comm on 64-bit Apple OSes.","shortMessageHtmlLink":"arm/arm-xlate.pl: handle .comm on 64-bit Apple OSes."}},{"before":"2c7a70025f15a751fef2ca793c64407ccb79cbd4","after":"d5f40a698b9087808399166cf7cdbe46ed493cc5","ref":"refs/heads/master","pushedAt":"2023-06-01T10:40:40.154Z","pushType":"push","commitsCount":2,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"x86_64/x86_64-xlate.pl: refine pre-processor handling on Win64.","shortMessageHtmlLink":"x86_64/x86_64-xlate.pl: refine pre-processor handling on Win64."}},{"before":"867aead87c00126f364548adf337cddc4ebccb9c","after":"2c7a70025f15a751fef2ca793c64407ccb79cbd4","ref":"refs/heads/master","pushedAt":"2023-05-28T16:43:05.328Z","pushType":"push","commitsCount":4,"pusher":{"login":"dot-asm","name":"Andy Polyakov","path":"/dot-asm","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/9038069?s=80&v=4"},"commit":{"message":"x86_64/x86_64-xlate.pl: handle .comm as .global.","shortMessageHtmlLink":"x86_64/x86_64-xlate.pl: handle .comm as .global."}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEWyfKzwA","startCursor":null,"endCursor":null}},"title":"Activity ยท dot-asm/cryptogams"}