diff --git a/conf.py b/conf.py
index e88ecd7..9b685d7 100644
--- a/conf.py
+++ b/conf.py
@@ -176,10 +176,10 @@ def _LatestTagName():
 # Sphinx.Ext.InterSphinx
 # ==============================================================================
 intersphinx_mapping = {
-	'python':               ('https://docs.python.org/3', None),
-	'osvb':                 ('https://umarcor.github.io/osvb', None),
-	'pyVHDLModel':          ('https://vhdl.github.io/pyVHDLModel', None),
-	'pySystemVerilogModel': ('https://edaa-org.github.io/pySystemVerilogModel', None),
+	'python':    ('https://docs.python.org/3', None),
+	'osvb':      ('https://umarcor.github.io/osvb', None),
+	'vhdlmodel': ('https://vhdl.github.io/pyVHDLModel', None),
+	'svmodel':   ('https://edaa-org.github.io/pySystemVerilogModel', None),
 }