/
ztypes_arm_unix.go
919 lines (891 loc) · 30.2 KB
/
ztypes_arm_unix.go
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// Code generated by cmd/cgo -godefs; DO NOT EDIT.
// cgo -godefs types_arm_unix.go
package capstone
type ArmCc uint32
const (
ARM_CC_INVALID ArmCc = 0x0
ARM_CC_EQ ArmCc = 0x1
ARM_CC_NE ArmCc = 0x2
ARM_CC_HS ArmCc = 0x3
ARM_CC_LO ArmCc = 0x4
ARM_CC_MI ArmCc = 0x5
ARM_CC_PL ArmCc = 0x6
ARM_CC_VS ArmCc = 0x7
ARM_CC_VC ArmCc = 0x8
ARM_CC_HI ArmCc = 0x9
ARM_CC_LS ArmCc = 0xa
ARM_CC_GE ArmCc = 0xb
ARM_CC_LT ArmCc = 0xc
ARM_CC_GT ArmCc = 0xd
ARM_CC_LE ArmCc = 0xe
ARM_CC_AL ArmCc = 0xf
)
type ArmCpsflagType uint32
const (
ARM_CPSFLAG_INVALID ArmCpsflagType = 0x0
ARM_CPSFLAG_F ArmCpsflagType = 0x1
ARM_CPSFLAG_I ArmCpsflagType = 0x2
ARM_CPSFLAG_A ArmCpsflagType = 0x4
ARM_CPSFLAG_NONE ArmCpsflagType = 0x10
)
type ArmCpsmodeType uint32
const (
ARM_CPSMODE_INVALID ArmCpsmodeType = 0x0
ARM_CPSMODE_IE ArmCpsmodeType = 0x2
ARM_CPSMODE_ID ArmCpsmodeType = 0x3
)
type ArmInsn uint32
const (
ARM_INS_INVALID ArmInsn = 0x0
ARM_INS_ADC ArmInsn = 0x1
ARM_INS_ADD ArmInsn = 0x2
ARM_INS_ADDW ArmInsn = 0x3
ARM_INS_ADR ArmInsn = 0x4
ARM_INS_AESD ArmInsn = 0x5
ARM_INS_AESE ArmInsn = 0x6
ARM_INS_AESIMC ArmInsn = 0x7
ARM_INS_AESMC ArmInsn = 0x8
ARM_INS_AND ArmInsn = 0x9
ARM_INS_ASR ArmInsn = 0xa
ARM_INS_B ArmInsn = 0xb
ARM_INS_BFC ArmInsn = 0xc
ARM_INS_BFI ArmInsn = 0xd
ARM_INS_BIC ArmInsn = 0xe
ARM_INS_BKPT ArmInsn = 0xf
ARM_INS_BL ArmInsn = 0x10
ARM_INS_BLX ArmInsn = 0x11
ARM_INS_BLXNS ArmInsn = 0x12
ARM_INS_BX ArmInsn = 0x13
ARM_INS_BXJ ArmInsn = 0x14
ARM_INS_BXNS ArmInsn = 0x15
ARM_INS_CBNZ ArmInsn = 0x16
ARM_INS_CBZ ArmInsn = 0x17
ARM_INS_CDP ArmInsn = 0x18
ARM_INS_CDP2 ArmInsn = 0x19
ARM_INS_CLREX ArmInsn = 0x1a
ARM_INS_CLZ ArmInsn = 0x1b
ARM_INS_CMN ArmInsn = 0x1c
ARM_INS_CMP ArmInsn = 0x1d
ARM_INS_CPS ArmInsn = 0x1e
ARM_INS_CRC32B ArmInsn = 0x1f
ARM_INS_CRC32CB ArmInsn = 0x20
ARM_INS_CRC32CH ArmInsn = 0x21
ARM_INS_CRC32CW ArmInsn = 0x22
ARM_INS_CRC32H ArmInsn = 0x23
ARM_INS_CRC32W ArmInsn = 0x24
ARM_INS_CSDB ArmInsn = 0x25
ARM_INS_DBG ArmInsn = 0x26
ARM_INS_DCPS1 ArmInsn = 0x27
ARM_INS_DCPS2 ArmInsn = 0x28
ARM_INS_DCPS3 ArmInsn = 0x29
ARM_INS_DFB ArmInsn = 0x2a
ARM_INS_DMB ArmInsn = 0x2b
ARM_INS_DSB ArmInsn = 0x2c
ARM_INS_EOR ArmInsn = 0x2d
ARM_INS_ERET ArmInsn = 0x2e
ARM_INS_ESB ArmInsn = 0x2f
ARM_INS_FADDD ArmInsn = 0x30
ARM_INS_FADDS ArmInsn = 0x31
ARM_INS_FCMPZD ArmInsn = 0x32
ARM_INS_FCMPZS ArmInsn = 0x33
ARM_INS_FCONSTD ArmInsn = 0x34
ARM_INS_FCONSTS ArmInsn = 0x35
ARM_INS_FLDMDBX ArmInsn = 0x36
ARM_INS_FLDMIAX ArmInsn = 0x37
ARM_INS_FMDHR ArmInsn = 0x38
ARM_INS_FMDLR ArmInsn = 0x39
ARM_INS_FMSTAT ArmInsn = 0x3a
ARM_INS_FSTMDBX ArmInsn = 0x3b
ARM_INS_FSTMIAX ArmInsn = 0x3c
ARM_INS_FSUBD ArmInsn = 0x3d
ARM_INS_FSUBS ArmInsn = 0x3e
ARM_INS_HINT ArmInsn = 0x3f
ARM_INS_HLT ArmInsn = 0x40
ARM_INS_HVC ArmInsn = 0x41
ARM_INS_ISB ArmInsn = 0x42
ARM_INS_IT ArmInsn = 0x43
ARM_INS_LDA ArmInsn = 0x44
ARM_INS_LDAB ArmInsn = 0x45
ARM_INS_LDAEX ArmInsn = 0x46
ARM_INS_LDAEXB ArmInsn = 0x47
ARM_INS_LDAEXD ArmInsn = 0x48
ARM_INS_LDAEXH ArmInsn = 0x49
ARM_INS_LDAH ArmInsn = 0x4a
ARM_INS_LDC ArmInsn = 0x4b
ARM_INS_LDC2 ArmInsn = 0x4c
ARM_INS_LDC2L ArmInsn = 0x4d
ARM_INS_LDCL ArmInsn = 0x4e
ARM_INS_LDM ArmInsn = 0x4f
ARM_INS_LDMDA ArmInsn = 0x50
ARM_INS_LDMDB ArmInsn = 0x51
ARM_INS_LDMIB ArmInsn = 0x52
ARM_INS_LDR ArmInsn = 0x53
ARM_INS_LDRB ArmInsn = 0x54
ARM_INS_LDRBT ArmInsn = 0x55
ARM_INS_LDRD ArmInsn = 0x56
ARM_INS_LDREX ArmInsn = 0x57
ARM_INS_LDREXB ArmInsn = 0x58
ARM_INS_LDREXD ArmInsn = 0x59
ARM_INS_LDREXH ArmInsn = 0x5a
ARM_INS_LDRH ArmInsn = 0x5b
ARM_INS_LDRHT ArmInsn = 0x5c
ARM_INS_LDRSB ArmInsn = 0x5d
ARM_INS_LDRSBT ArmInsn = 0x5e
ARM_INS_LDRSH ArmInsn = 0x5f
ARM_INS_LDRSHT ArmInsn = 0x60
ARM_INS_LDRT ArmInsn = 0x61
ARM_INS_LSL ArmInsn = 0x62
ARM_INS_LSR ArmInsn = 0x63
ARM_INS_MCR ArmInsn = 0x64
ARM_INS_MCR2 ArmInsn = 0x65
ARM_INS_MCRR ArmInsn = 0x66
ARM_INS_MCRR2 ArmInsn = 0x67
ARM_INS_MLA ArmInsn = 0x68
ARM_INS_MLS ArmInsn = 0x69
ARM_INS_MOV ArmInsn = 0x6a
ARM_INS_MOVS ArmInsn = 0x6b
ARM_INS_MOVT ArmInsn = 0x6c
ARM_INS_MOVW ArmInsn = 0x6d
ARM_INS_MRC ArmInsn = 0x6e
ARM_INS_MRC2 ArmInsn = 0x6f
ARM_INS_MRRC ArmInsn = 0x70
ARM_INS_MRRC2 ArmInsn = 0x71
ARM_INS_MRS ArmInsn = 0x72
ARM_INS_MSR ArmInsn = 0x73
ARM_INS_MUL ArmInsn = 0x74
ARM_INS_MVN ArmInsn = 0x75
ARM_INS_NEG ArmInsn = 0x76
ARM_INS_NOP ArmInsn = 0x77
ARM_INS_ORN ArmInsn = 0x78
ARM_INS_ORR ArmInsn = 0x79
ARM_INS_PKHBT ArmInsn = 0x7a
ARM_INS_PKHTB ArmInsn = 0x7b
ARM_INS_PLD ArmInsn = 0x7c
ARM_INS_PLDW ArmInsn = 0x7d
ARM_INS_PLI ArmInsn = 0x7e
ARM_INS_POP ArmInsn = 0x7f
ARM_INS_PUSH ArmInsn = 0x80
ARM_INS_QADD ArmInsn = 0x81
ARM_INS_QADD16 ArmInsn = 0x82
ARM_INS_QADD8 ArmInsn = 0x83
ARM_INS_QASX ArmInsn = 0x84
ARM_INS_QDADD ArmInsn = 0x85
ARM_INS_QDSUB ArmInsn = 0x86
ARM_INS_QSAX ArmInsn = 0x87
ARM_INS_QSUB ArmInsn = 0x88
ARM_INS_QSUB16 ArmInsn = 0x89
ARM_INS_QSUB8 ArmInsn = 0x8a
ARM_INS_RBIT ArmInsn = 0x8b
ARM_INS_REV ArmInsn = 0x8c
ARM_INS_REV16 ArmInsn = 0x8d
ARM_INS_REVSH ArmInsn = 0x8e
ARM_INS_RFEDA ArmInsn = 0x8f
ARM_INS_RFEDB ArmInsn = 0x90
ARM_INS_RFEIA ArmInsn = 0x91
ARM_INS_RFEIB ArmInsn = 0x92
ARM_INS_ROR ArmInsn = 0x93
ARM_INS_RRX ArmInsn = 0x94
ARM_INS_RSB ArmInsn = 0x95
ARM_INS_RSC ArmInsn = 0x96
ARM_INS_SADD16 ArmInsn = 0x97
ARM_INS_SADD8 ArmInsn = 0x98
ARM_INS_SASX ArmInsn = 0x99
ARM_INS_SBC ArmInsn = 0x9a
ARM_INS_SBFX ArmInsn = 0x9b
ARM_INS_SDIV ArmInsn = 0x9c
ARM_INS_SEL ArmInsn = 0x9d
ARM_INS_SETEND ArmInsn = 0x9e
ARM_INS_SETPAN ArmInsn = 0x9f
ARM_INS_SEV ArmInsn = 0xa0
ARM_INS_SEVL ArmInsn = 0xa1
ARM_INS_SG ArmInsn = 0xa2
ARM_INS_SHA1C ArmInsn = 0xa3
ARM_INS_SHA1H ArmInsn = 0xa4
ARM_INS_SHA1M ArmInsn = 0xa5
ARM_INS_SHA1P ArmInsn = 0xa6
ARM_INS_SHA1SU0 ArmInsn = 0xa7
ARM_INS_SHA1SU1 ArmInsn = 0xa8
ARM_INS_SHA256H ArmInsn = 0xa9
ARM_INS_SHA256H2 ArmInsn = 0xaa
ARM_INS_SHA256SU0 ArmInsn = 0xab
ARM_INS_SHA256SU1 ArmInsn = 0xac
ARM_INS_SHADD16 ArmInsn = 0xad
ARM_INS_SHADD8 ArmInsn = 0xae
ARM_INS_SHASX ArmInsn = 0xaf
ARM_INS_SHSAX ArmInsn = 0xb0
ARM_INS_SHSUB16 ArmInsn = 0xb1
ARM_INS_SHSUB8 ArmInsn = 0xb2
ARM_INS_SMC ArmInsn = 0xb3
ARM_INS_SMLABB ArmInsn = 0xb4
ARM_INS_SMLABT ArmInsn = 0xb5
ARM_INS_SMLAD ArmInsn = 0xb6
ARM_INS_SMLADX ArmInsn = 0xb7
ARM_INS_SMLAL ArmInsn = 0xb8
ARM_INS_SMLALBB ArmInsn = 0xb9
ARM_INS_SMLALBT ArmInsn = 0xba
ARM_INS_SMLALD ArmInsn = 0xbb
ARM_INS_SMLALDX ArmInsn = 0xbc
ARM_INS_SMLALTB ArmInsn = 0xbd
ARM_INS_SMLALTT ArmInsn = 0xbe
ARM_INS_SMLATB ArmInsn = 0xbf
ARM_INS_SMLATT ArmInsn = 0xc0
ARM_INS_SMLAWB ArmInsn = 0xc1
ARM_INS_SMLAWT ArmInsn = 0xc2
ARM_INS_SMLSD ArmInsn = 0xc3
ARM_INS_SMLSDX ArmInsn = 0xc4
ARM_INS_SMLSLD ArmInsn = 0xc5
ARM_INS_SMLSLDX ArmInsn = 0xc6
ARM_INS_SMMLA ArmInsn = 0xc7
ARM_INS_SMMLAR ArmInsn = 0xc8
ARM_INS_SMMLS ArmInsn = 0xc9
ARM_INS_SMMLSR ArmInsn = 0xca
ARM_INS_SMMUL ArmInsn = 0xcb
ARM_INS_SMMULR ArmInsn = 0xcc
ARM_INS_SMUAD ArmInsn = 0xcd
ARM_INS_SMUADX ArmInsn = 0xce
ARM_INS_SMULBB ArmInsn = 0xcf
ARM_INS_SMULBT ArmInsn = 0xd0
ARM_INS_SMULL ArmInsn = 0xd1
ARM_INS_SMULTB ArmInsn = 0xd2
ARM_INS_SMULTT ArmInsn = 0xd3
ARM_INS_SMULWB ArmInsn = 0xd4
ARM_INS_SMULWT ArmInsn = 0xd5
ARM_INS_SMUSD ArmInsn = 0xd6
ARM_INS_SMUSDX ArmInsn = 0xd7
ARM_INS_SRSDA ArmInsn = 0xd8
ARM_INS_SRSDB ArmInsn = 0xd9
ARM_INS_SRSIA ArmInsn = 0xda
ARM_INS_SRSIB ArmInsn = 0xdb
ARM_INS_SSAT ArmInsn = 0xdc
ARM_INS_SSAT16 ArmInsn = 0xdd
ARM_INS_SSAX ArmInsn = 0xde
ARM_INS_SSUB16 ArmInsn = 0xdf
ARM_INS_SSUB8 ArmInsn = 0xe0
ARM_INS_STC ArmInsn = 0xe1
ARM_INS_STC2 ArmInsn = 0xe2
ARM_INS_STC2L ArmInsn = 0xe3
ARM_INS_STCL ArmInsn = 0xe4
ARM_INS_STL ArmInsn = 0xe5
ARM_INS_STLB ArmInsn = 0xe6
ARM_INS_STLEX ArmInsn = 0xe7
ARM_INS_STLEXB ArmInsn = 0xe8
ARM_INS_STLEXD ArmInsn = 0xe9
ARM_INS_STLEXH ArmInsn = 0xea
ARM_INS_STLH ArmInsn = 0xeb
ARM_INS_STM ArmInsn = 0xec
ARM_INS_STMDA ArmInsn = 0xed
ARM_INS_STMDB ArmInsn = 0xee
ARM_INS_STMIB ArmInsn = 0xef
ARM_INS_STR ArmInsn = 0xf0
ARM_INS_STRB ArmInsn = 0xf1
ARM_INS_STRBT ArmInsn = 0xf2
ARM_INS_STRD ArmInsn = 0xf3
ARM_INS_STREX ArmInsn = 0xf4
ARM_INS_STREXB ArmInsn = 0xf5
ARM_INS_STREXD ArmInsn = 0xf6
ARM_INS_STREXH ArmInsn = 0xf7
ARM_INS_STRH ArmInsn = 0xf8
ARM_INS_STRHT ArmInsn = 0xf9
ARM_INS_STRT ArmInsn = 0xfa
ARM_INS_SUB ArmInsn = 0xfb
ARM_INS_SUBS ArmInsn = 0xfc
ARM_INS_SUBW ArmInsn = 0xfd
ARM_INS_SVC ArmInsn = 0xfe
ARM_INS_SWP ArmInsn = 0xff
ARM_INS_SWPB ArmInsn = 0x100
ARM_INS_SXTAB ArmInsn = 0x101
ARM_INS_SXTAB16 ArmInsn = 0x102
ARM_INS_SXTAH ArmInsn = 0x103
ARM_INS_SXTB ArmInsn = 0x104
ARM_INS_SXTB16 ArmInsn = 0x105
ARM_INS_SXTH ArmInsn = 0x106
ARM_INS_TBB ArmInsn = 0x107
ARM_INS_TBH ArmInsn = 0x108
ARM_INS_TEQ ArmInsn = 0x109
ARM_INS_TRAP ArmInsn = 0x10a
ARM_INS_TSB ArmInsn = 0x10b
ARM_INS_TST ArmInsn = 0x10c
ARM_INS_TT ArmInsn = 0x10d
ARM_INS_TTA ArmInsn = 0x10e
ARM_INS_TTAT ArmInsn = 0x10f
ARM_INS_TTT ArmInsn = 0x110
ARM_INS_UADD16 ArmInsn = 0x111
ARM_INS_UADD8 ArmInsn = 0x112
ARM_INS_UASX ArmInsn = 0x113
ARM_INS_UBFX ArmInsn = 0x114
ARM_INS_UDF ArmInsn = 0x115
ARM_INS_UDIV ArmInsn = 0x116
ARM_INS_UHADD16 ArmInsn = 0x117
ARM_INS_UHADD8 ArmInsn = 0x118
ARM_INS_UHASX ArmInsn = 0x119
ARM_INS_UHSAX ArmInsn = 0x11a
ARM_INS_UHSUB16 ArmInsn = 0x11b
ARM_INS_UHSUB8 ArmInsn = 0x11c
ARM_INS_UMAAL ArmInsn = 0x11d
ARM_INS_UMLAL ArmInsn = 0x11e
ARM_INS_UMULL ArmInsn = 0x11f
ARM_INS_UQADD16 ArmInsn = 0x120
ARM_INS_UQADD8 ArmInsn = 0x121
ARM_INS_UQASX ArmInsn = 0x122
ARM_INS_UQSAX ArmInsn = 0x123
ARM_INS_UQSUB16 ArmInsn = 0x124
ARM_INS_UQSUB8 ArmInsn = 0x125
ARM_INS_USAD8 ArmInsn = 0x126
ARM_INS_USADA8 ArmInsn = 0x127
ARM_INS_USAT ArmInsn = 0x128
ARM_INS_USAT16 ArmInsn = 0x129
ARM_INS_USAX ArmInsn = 0x12a
ARM_INS_USUB16 ArmInsn = 0x12b
ARM_INS_USUB8 ArmInsn = 0x12c
ARM_INS_UXTAB ArmInsn = 0x12d
ARM_INS_UXTAB16 ArmInsn = 0x12e
ARM_INS_UXTAH ArmInsn = 0x12f
ARM_INS_UXTB ArmInsn = 0x130
ARM_INS_UXTB16 ArmInsn = 0x131
ARM_INS_UXTH ArmInsn = 0x132
ARM_INS_VABA ArmInsn = 0x133
ARM_INS_VABAL ArmInsn = 0x134
ARM_INS_VABD ArmInsn = 0x135
ARM_INS_VABDL ArmInsn = 0x136
ARM_INS_VABS ArmInsn = 0x137
ARM_INS_VACGE ArmInsn = 0x138
ARM_INS_VACGT ArmInsn = 0x139
ARM_INS_VACLE ArmInsn = 0x13a
ARM_INS_VACLT ArmInsn = 0x13b
ARM_INS_VADD ArmInsn = 0x13c
ARM_INS_VADDHN ArmInsn = 0x13d
ARM_INS_VADDL ArmInsn = 0x13e
ARM_INS_VADDW ArmInsn = 0x13f
ARM_INS_VAND ArmInsn = 0x140
ARM_INS_VBIC ArmInsn = 0x141
ARM_INS_VBIF ArmInsn = 0x142
ARM_INS_VBIT ArmInsn = 0x143
ARM_INS_VBSL ArmInsn = 0x144
ARM_INS_VCADD ArmInsn = 0x145
ARM_INS_VCEQ ArmInsn = 0x146
ARM_INS_VCGE ArmInsn = 0x147
ARM_INS_VCGT ArmInsn = 0x148
ARM_INS_VCLE ArmInsn = 0x149
ARM_INS_VCLS ArmInsn = 0x14a
ARM_INS_VCLT ArmInsn = 0x14b
ARM_INS_VCLZ ArmInsn = 0x14c
ARM_INS_VCMLA ArmInsn = 0x14d
ARM_INS_VCMP ArmInsn = 0x14e
ARM_INS_VCMPE ArmInsn = 0x14f
ARM_INS_VCNT ArmInsn = 0x150
ARM_INS_VCVT ArmInsn = 0x151
ARM_INS_VCVTA ArmInsn = 0x152
ARM_INS_VCVTB ArmInsn = 0x153
ARM_INS_VCVTM ArmInsn = 0x154
ARM_INS_VCVTN ArmInsn = 0x155
ARM_INS_VCVTP ArmInsn = 0x156
ARM_INS_VCVTR ArmInsn = 0x157
ARM_INS_VCVTT ArmInsn = 0x158
ARM_INS_VDIV ArmInsn = 0x159
ARM_INS_VDUP ArmInsn = 0x15a
ARM_INS_VEOR ArmInsn = 0x15b
ARM_INS_VEXT ArmInsn = 0x15c
ARM_INS_VFMA ArmInsn = 0x15d
ARM_INS_VFMS ArmInsn = 0x15e
ARM_INS_VFNMA ArmInsn = 0x15f
ARM_INS_VFNMS ArmInsn = 0x160
ARM_INS_VHADD ArmInsn = 0x161
ARM_INS_VHSUB ArmInsn = 0x162
ARM_INS_VINS ArmInsn = 0x163
ARM_INS_VJCVT ArmInsn = 0x164
ARM_INS_VLD1 ArmInsn = 0x165
ARM_INS_VLD2 ArmInsn = 0x166
ARM_INS_VLD3 ArmInsn = 0x167
ARM_INS_VLD4 ArmInsn = 0x168
ARM_INS_VLDMDB ArmInsn = 0x169
ARM_INS_VLDMIA ArmInsn = 0x16a
ARM_INS_VLDR ArmInsn = 0x16b
ARM_INS_VLLDM ArmInsn = 0x16c
ARM_INS_VLSTM ArmInsn = 0x16d
ARM_INS_VMAX ArmInsn = 0x16e
ARM_INS_VMAXNM ArmInsn = 0x16f
ARM_INS_VMIN ArmInsn = 0x170
ARM_INS_VMINNM ArmInsn = 0x171
ARM_INS_VMLA ArmInsn = 0x172
ARM_INS_VMLAL ArmInsn = 0x173
ARM_INS_VMLS ArmInsn = 0x174
ARM_INS_VMLSL ArmInsn = 0x175
ARM_INS_VMOV ArmInsn = 0x176
ARM_INS_VMOVL ArmInsn = 0x177
ARM_INS_VMOVN ArmInsn = 0x178
ARM_INS_VMOVX ArmInsn = 0x179
ARM_INS_VMRS ArmInsn = 0x17a
ARM_INS_VMSR ArmInsn = 0x17b
ARM_INS_VMUL ArmInsn = 0x17c
ARM_INS_VMULL ArmInsn = 0x17d
ARM_INS_VMVN ArmInsn = 0x17e
ARM_INS_VNEG ArmInsn = 0x17f
ARM_INS_VNMLA ArmInsn = 0x180
ARM_INS_VNMLS ArmInsn = 0x181
ARM_INS_VNMUL ArmInsn = 0x182
ARM_INS_VORN ArmInsn = 0x183
ARM_INS_VORR ArmInsn = 0x184
ARM_INS_VPADAL ArmInsn = 0x185
ARM_INS_VPADD ArmInsn = 0x186
ARM_INS_VPADDL ArmInsn = 0x187
ARM_INS_VPMAX ArmInsn = 0x188
ARM_INS_VPMIN ArmInsn = 0x189
ARM_INS_VPOP ArmInsn = 0x18a
ARM_INS_VPUSH ArmInsn = 0x18b
ARM_INS_VQABS ArmInsn = 0x18c
ARM_INS_VQADD ArmInsn = 0x18d
ARM_INS_VQDMLAL ArmInsn = 0x18e
ARM_INS_VQDMLSL ArmInsn = 0x18f
ARM_INS_VQDMULH ArmInsn = 0x190
ARM_INS_VQDMULL ArmInsn = 0x191
ARM_INS_VQMOVN ArmInsn = 0x192
ARM_INS_VQMOVUN ArmInsn = 0x193
ARM_INS_VQNEG ArmInsn = 0x194
ARM_INS_VQRDMLAH ArmInsn = 0x195
ARM_INS_VQRDMLSH ArmInsn = 0x196
ARM_INS_VQRDMULH ArmInsn = 0x197
ARM_INS_VQRSHL ArmInsn = 0x198
ARM_INS_VQRSHRN ArmInsn = 0x199
ARM_INS_VQRSHRUN ArmInsn = 0x19a
ARM_INS_VQSHL ArmInsn = 0x19b
ARM_INS_VQSHLU ArmInsn = 0x19c
ARM_INS_VQSHRN ArmInsn = 0x19d
ARM_INS_VQSHRUN ArmInsn = 0x19e
ARM_INS_VQSUB ArmInsn = 0x19f
ARM_INS_VRADDHN ArmInsn = 0x1a0
ARM_INS_VRECPE ArmInsn = 0x1a1
ARM_INS_VRECPS ArmInsn = 0x1a2
ARM_INS_VREV16 ArmInsn = 0x1a3
ARM_INS_VREV32 ArmInsn = 0x1a4
ARM_INS_VREV64 ArmInsn = 0x1a5
ARM_INS_VRHADD ArmInsn = 0x1a6
ARM_INS_VRINTA ArmInsn = 0x1a7
ARM_INS_VRINTM ArmInsn = 0x1a8
ARM_INS_VRINTN ArmInsn = 0x1a9
ARM_INS_VRINTP ArmInsn = 0x1aa
ARM_INS_VRINTR ArmInsn = 0x1ab
ARM_INS_VRINTX ArmInsn = 0x1ac
ARM_INS_VRINTZ ArmInsn = 0x1ad
ARM_INS_VRSHL ArmInsn = 0x1ae
ARM_INS_VRSHR ArmInsn = 0x1af
ARM_INS_VRSHRN ArmInsn = 0x1b0
ARM_INS_VRSQRTE ArmInsn = 0x1b1
ARM_INS_VRSQRTS ArmInsn = 0x1b2
ARM_INS_VRSRA ArmInsn = 0x1b3
ARM_INS_VRSUBHN ArmInsn = 0x1b4
ARM_INS_VSDOT ArmInsn = 0x1b5
ARM_INS_VSELEQ ArmInsn = 0x1b6
ARM_INS_VSELGE ArmInsn = 0x1b7
ARM_INS_VSELGT ArmInsn = 0x1b8
ARM_INS_VSELVS ArmInsn = 0x1b9
ARM_INS_VSHL ArmInsn = 0x1ba
ARM_INS_VSHLL ArmInsn = 0x1bb
ARM_INS_VSHR ArmInsn = 0x1bc
ARM_INS_VSHRN ArmInsn = 0x1bd
ARM_INS_VSLI ArmInsn = 0x1be
ARM_INS_VSQRT ArmInsn = 0x1bf
ARM_INS_VSRA ArmInsn = 0x1c0
ARM_INS_VSRI ArmInsn = 0x1c1
ARM_INS_VST1 ArmInsn = 0x1c2
ARM_INS_VST2 ArmInsn = 0x1c3
ARM_INS_VST3 ArmInsn = 0x1c4
ARM_INS_VST4 ArmInsn = 0x1c5
ARM_INS_VSTMDB ArmInsn = 0x1c6
ARM_INS_VSTMIA ArmInsn = 0x1c7
ARM_INS_VSTR ArmInsn = 0x1c8
ARM_INS_VSUB ArmInsn = 0x1c9
ARM_INS_VSUBHN ArmInsn = 0x1ca
ARM_INS_VSUBL ArmInsn = 0x1cb
ARM_INS_VSUBW ArmInsn = 0x1cc
ARM_INS_VSWP ArmInsn = 0x1cd
ARM_INS_VTBL ArmInsn = 0x1ce
ARM_INS_VTBX ArmInsn = 0x1cf
ARM_INS_VTRN ArmInsn = 0x1d0
ARM_INS_VTST ArmInsn = 0x1d1
ARM_INS_VUDOT ArmInsn = 0x1d2
ARM_INS_VUZP ArmInsn = 0x1d3
ARM_INS_VZIP ArmInsn = 0x1d4
ARM_INS_WFE ArmInsn = 0x1d5
ARM_INS_WFI ArmInsn = 0x1d6
ARM_INS_YIELD ArmInsn = 0x1d7
ARM_INS_ENDING ArmInsn = 0x1d8
)
type ArmInsnGroup uint32
const (
ARM_GRP_INVALID ArmInsnGroup = 0x0
ARM_GRP_JUMP ArmInsnGroup = 0x1
ARM_GRP_CALL ArmInsnGroup = 0x2
ARM_GRP_INT ArmInsnGroup = 0x4
ARM_GRP_PRIVILEGE ArmInsnGroup = 0x6
ARM_GRP_BRANCH_RELATIVE ArmInsnGroup = 0x7
ARM_GRP_CRYPTO ArmInsnGroup = 0x80
ARM_GRP_DATABARRIER ArmInsnGroup = 0x81
ARM_GRP_DIVIDE ArmInsnGroup = 0x82
ARM_GRP_FPARMV8 ArmInsnGroup = 0x83
ARM_GRP_MULTPRO ArmInsnGroup = 0x84
ARM_GRP_NEON ArmInsnGroup = 0x85
ARM_GRP_T2EXTRACTPACK ArmInsnGroup = 0x86
ARM_GRP_THUMB2DSP ArmInsnGroup = 0x87
ARM_GRP_TRUSTZONE ArmInsnGroup = 0x88
ARM_GRP_V4T ArmInsnGroup = 0x89
ARM_GRP_V5T ArmInsnGroup = 0x8a
ARM_GRP_V5TE ArmInsnGroup = 0x8b
ARM_GRP_V6 ArmInsnGroup = 0x8c
ARM_GRP_V6T2 ArmInsnGroup = 0x8d
ARM_GRP_V7 ArmInsnGroup = 0x8e
ARM_GRP_V8 ArmInsnGroup = 0x8f
ARM_GRP_VFP2 ArmInsnGroup = 0x90
ARM_GRP_VFP3 ArmInsnGroup = 0x91
ARM_GRP_VFP4 ArmInsnGroup = 0x92
ARM_GRP_ARM ArmInsnGroup = 0x93
ARM_GRP_MCLASS ArmInsnGroup = 0x94
ARM_GRP_NOTMCLASS ArmInsnGroup = 0x95
ARM_GRP_THUMB ArmInsnGroup = 0x96
ARM_GRP_THUMB1ONLY ArmInsnGroup = 0x97
ARM_GRP_THUMB2 ArmInsnGroup = 0x98
ARM_GRP_PREV8 ArmInsnGroup = 0x99
ARM_GRP_FPVMLX ArmInsnGroup = 0x9a
ARM_GRP_MULOPS ArmInsnGroup = 0x9b
ARM_GRP_CRC ArmInsnGroup = 0x9c
ARM_GRP_DPVFP ArmInsnGroup = 0x9d
ARM_GRP_V6M ArmInsnGroup = 0x9e
ARM_GRP_VIRTUALIZATION ArmInsnGroup = 0x9f
ARM_GRP_ENDING ArmInsnGroup = 0xa0
)
type ArmMemBarrier uint32
const (
ARM_MB_INVALID ArmMemBarrier = 0x0
ARM_MB_RESERVED_0 ArmMemBarrier = 0x1
ARM_MB_OSHLD ArmMemBarrier = 0x2
ARM_MB_OSHST ArmMemBarrier = 0x3
ARM_MB_OSH ArmMemBarrier = 0x4
ARM_MB_RESERVED_4 ArmMemBarrier = 0x5
ARM_MB_NSHLD ArmMemBarrier = 0x6
ARM_MB_NSHST ArmMemBarrier = 0x7
ARM_MB_NSH ArmMemBarrier = 0x8
ARM_MB_RESERVED_8 ArmMemBarrier = 0x9
ARM_MB_ISHLD ArmMemBarrier = 0xa
ARM_MB_ISHST ArmMemBarrier = 0xb
ARM_MB_ISH ArmMemBarrier = 0xc
ARM_MB_RESERVED_12 ArmMemBarrier = 0xd
ARM_MB_LD ArmMemBarrier = 0xe
ARM_MB_ST ArmMemBarrier = 0xf
ARM_MB_SY ArmMemBarrier = 0x10
)
type ArmOpType uint32
const (
ARM_OP_INVALID ArmOpType = 0x0
ARM_OP_REG ArmOpType = 0x1
ARM_OP_IMM ArmOpType = 0x2
ARM_OP_MEM ArmOpType = 0x3
ARM_OP_FP ArmOpType = 0x4
ARM_OP_CIMM ArmOpType = 0x40
ARM_OP_PIMM ArmOpType = 0x41
ARM_OP_SETEND ArmOpType = 0x42
ARM_OP_SYSREG ArmOpType = 0x43
)
type ArmReg uint32
const (
ARM_REG_INVALID ArmReg = 0x0
ARM_REG_APSR ArmReg = 0x1
ARM_REG_APSR_NZCV ArmReg = 0x2
ARM_REG_CPSR ArmReg = 0x3
ARM_REG_FPEXC ArmReg = 0x4
ARM_REG_FPINST ArmReg = 0x5
ARM_REG_FPSCR ArmReg = 0x6
ARM_REG_FPSCR_NZCV ArmReg = 0x7
ARM_REG_FPSID ArmReg = 0x8
ARM_REG_ITSTATE ArmReg = 0x9
ARM_REG_LR ArmReg = 0xa
ARM_REG_PC ArmReg = 0xb
ARM_REG_SP ArmReg = 0xc
ARM_REG_SPSR ArmReg = 0xd
ARM_REG_D0 ArmReg = 0xe
ARM_REG_D1 ArmReg = 0xf
ARM_REG_D2 ArmReg = 0x10
ARM_REG_D3 ArmReg = 0x11
ARM_REG_D4 ArmReg = 0x12
ARM_REG_D5 ArmReg = 0x13
ARM_REG_D6 ArmReg = 0x14
ARM_REG_D7 ArmReg = 0x15
ARM_REG_D8 ArmReg = 0x16
ARM_REG_D9 ArmReg = 0x17
ARM_REG_D10 ArmReg = 0x18
ARM_REG_D11 ArmReg = 0x19
ARM_REG_D12 ArmReg = 0x1a
ARM_REG_D13 ArmReg = 0x1b
ARM_REG_D14 ArmReg = 0x1c
ARM_REG_D15 ArmReg = 0x1d
ARM_REG_D16 ArmReg = 0x1e
ARM_REG_D17 ArmReg = 0x1f
ARM_REG_D18 ArmReg = 0x20
ARM_REG_D19 ArmReg = 0x21
ARM_REG_D20 ArmReg = 0x22
ARM_REG_D21 ArmReg = 0x23
ARM_REG_D22 ArmReg = 0x24
ARM_REG_D23 ArmReg = 0x25
ARM_REG_D24 ArmReg = 0x26
ARM_REG_D25 ArmReg = 0x27
ARM_REG_D26 ArmReg = 0x28
ARM_REG_D27 ArmReg = 0x29
ARM_REG_D28 ArmReg = 0x2a
ARM_REG_D29 ArmReg = 0x2b
ARM_REG_D30 ArmReg = 0x2c
ARM_REG_D31 ArmReg = 0x2d
ARM_REG_FPINST2 ArmReg = 0x2e
ARM_REG_MVFR0 ArmReg = 0x2f
ARM_REG_MVFR1 ArmReg = 0x30
ARM_REG_MVFR2 ArmReg = 0x31
ARM_REG_Q0 ArmReg = 0x32
ARM_REG_Q1 ArmReg = 0x33
ARM_REG_Q2 ArmReg = 0x34
ARM_REG_Q3 ArmReg = 0x35
ARM_REG_Q4 ArmReg = 0x36
ARM_REG_Q5 ArmReg = 0x37
ARM_REG_Q6 ArmReg = 0x38
ARM_REG_Q7 ArmReg = 0x39
ARM_REG_Q8 ArmReg = 0x3a
ARM_REG_Q9 ArmReg = 0x3b
ARM_REG_Q10 ArmReg = 0x3c
ARM_REG_Q11 ArmReg = 0x3d
ARM_REG_Q12 ArmReg = 0x3e
ARM_REG_Q13 ArmReg = 0x3f
ARM_REG_Q14 ArmReg = 0x40
ARM_REG_Q15 ArmReg = 0x41
ARM_REG_R0 ArmReg = 0x42
ARM_REG_R1 ArmReg = 0x43
ARM_REG_R2 ArmReg = 0x44
ARM_REG_R3 ArmReg = 0x45
ARM_REG_R4 ArmReg = 0x46
ARM_REG_R5 ArmReg = 0x47
ARM_REG_R6 ArmReg = 0x48
ARM_REG_R7 ArmReg = 0x49
ARM_REG_R8 ArmReg = 0x4a
ARM_REG_R9 ArmReg = 0x4b
ARM_REG_R10 ArmReg = 0x4c
ARM_REG_R11 ArmReg = 0x4d
ARM_REG_R12 ArmReg = 0x4e
ARM_REG_S0 ArmReg = 0x4f
ARM_REG_S1 ArmReg = 0x50
ARM_REG_S2 ArmReg = 0x51
ARM_REG_S3 ArmReg = 0x52
ARM_REG_S4 ArmReg = 0x53
ARM_REG_S5 ArmReg = 0x54
ARM_REG_S6 ArmReg = 0x55
ARM_REG_S7 ArmReg = 0x56
ARM_REG_S8 ArmReg = 0x57
ARM_REG_S9 ArmReg = 0x58
ARM_REG_S10 ArmReg = 0x59
ARM_REG_S11 ArmReg = 0x5a
ARM_REG_S12 ArmReg = 0x5b
ARM_REG_S13 ArmReg = 0x5c
ARM_REG_S14 ArmReg = 0x5d
ARM_REG_S15 ArmReg = 0x5e
ARM_REG_S16 ArmReg = 0x5f
ARM_REG_S17 ArmReg = 0x60
ARM_REG_S18 ArmReg = 0x61
ARM_REG_S19 ArmReg = 0x62
ARM_REG_S20 ArmReg = 0x63
ARM_REG_S21 ArmReg = 0x64
ARM_REG_S22 ArmReg = 0x65
ARM_REG_S23 ArmReg = 0x66
ARM_REG_S24 ArmReg = 0x67
ARM_REG_S25 ArmReg = 0x68
ARM_REG_S26 ArmReg = 0x69
ARM_REG_S27 ArmReg = 0x6a
ARM_REG_S28 ArmReg = 0x6b
ARM_REG_S29 ArmReg = 0x6c
ARM_REG_S30 ArmReg = 0x6d
ARM_REG_S31 ArmReg = 0x6e
ARM_REG_ENDING ArmReg = 0x6f
ARM_REG_R13 ArmReg = 0xc
ARM_REG_R14 ArmReg = 0xa
ARM_REG_R15 ArmReg = 0xb
ARM_REG_SB ArmReg = 0x4b
ARM_REG_SL ArmReg = 0x4c
ARM_REG_FP ArmReg = 0x4d
ARM_REG_IP ArmReg = 0x4e
)
type ArmSetendType uint32
const (
ARM_SETEND_INVALID ArmSetendType = 0x0
ARM_SETEND_BE ArmSetendType = 0x1
ARM_SETEND_LE ArmSetendType = 0x2
)
type ArmShifter uint32
const (
ARM_SFT_INVALID ArmShifter = 0x0
ARM_SFT_ASR ArmShifter = 0x1
ARM_SFT_LSL ArmShifter = 0x2
ARM_SFT_LSR ArmShifter = 0x3
ARM_SFT_ROR ArmShifter = 0x4
ARM_SFT_RRX ArmShifter = 0x5
ARM_SFT_ASR_REG ArmShifter = 0x6
ARM_SFT_LSL_REG ArmShifter = 0x7
ARM_SFT_LSR_REG ArmShifter = 0x8
ARM_SFT_ROR_REG ArmShifter = 0x9
ARM_SFT_RRX_REG ArmShifter = 0xa
)
type ArmSysreg uint32
const (
ARM_SYSREG_INVALID ArmSysreg = 0x0
ARM_SYSREG_SPSR_C ArmSysreg = 0x1
ARM_SYSREG_SPSR_X ArmSysreg = 0x2
ARM_SYSREG_SPSR_S ArmSysreg = 0x4
ARM_SYSREG_SPSR_F ArmSysreg = 0x8
ARM_SYSREG_CPSR_C ArmSysreg = 0x10
ARM_SYSREG_CPSR_X ArmSysreg = 0x20
ARM_SYSREG_CPSR_S ArmSysreg = 0x40
ARM_SYSREG_CPSR_F ArmSysreg = 0x80
ARM_SYSREG_APSR ArmSysreg = 0x100
ARM_SYSREG_APSR_G ArmSysreg = 0x101
ARM_SYSREG_APSR_NZCVQ ArmSysreg = 0x102
ARM_SYSREG_APSR_NZCVQG ArmSysreg = 0x103
ARM_SYSREG_IAPSR ArmSysreg = 0x104
ARM_SYSREG_IAPSR_G ArmSysreg = 0x105
ARM_SYSREG_IAPSR_NZCVQG ArmSysreg = 0x106
ARM_SYSREG_IAPSR_NZCVQ ArmSysreg = 0x107
ARM_SYSREG_EAPSR ArmSysreg = 0x108
ARM_SYSREG_EAPSR_G ArmSysreg = 0x109
ARM_SYSREG_EAPSR_NZCVQG ArmSysreg = 0x10a
ARM_SYSREG_EAPSR_NZCVQ ArmSysreg = 0x10b
ARM_SYSREG_XPSR ArmSysreg = 0x10c
ARM_SYSREG_XPSR_G ArmSysreg = 0x10d
ARM_SYSREG_XPSR_NZCVQG ArmSysreg = 0x10e
ARM_SYSREG_XPSR_NZCVQ ArmSysreg = 0x10f
ARM_SYSREG_IPSR ArmSysreg = 0x110
ARM_SYSREG_EPSR ArmSysreg = 0x111
ARM_SYSREG_IEPSR ArmSysreg = 0x112
ARM_SYSREG_MSP ArmSysreg = 0x113
ARM_SYSREG_PSP ArmSysreg = 0x114
ARM_SYSREG_PRIMASK ArmSysreg = 0x115
ARM_SYSREG_BASEPRI ArmSysreg = 0x116
ARM_SYSREG_BASEPRI_MAX ArmSysreg = 0x117
ARM_SYSREG_FAULTMASK ArmSysreg = 0x118
ARM_SYSREG_CONTROL ArmSysreg = 0x119
ARM_SYSREG_MSPLIM ArmSysreg = 0x11a
ARM_SYSREG_PSPLIM ArmSysreg = 0x11b
ARM_SYSREG_MSP_NS ArmSysreg = 0x11c
ARM_SYSREG_PSP_NS ArmSysreg = 0x11d
ARM_SYSREG_MSPLIM_NS ArmSysreg = 0x11e
ARM_SYSREG_PSPLIM_NS ArmSysreg = 0x11f
ARM_SYSREG_PRIMASK_NS ArmSysreg = 0x120
ARM_SYSREG_BASEPRI_NS ArmSysreg = 0x121
ARM_SYSREG_FAULTMASK_NS ArmSysreg = 0x122
ARM_SYSREG_CONTROL_NS ArmSysreg = 0x123
ARM_SYSREG_SP_NS ArmSysreg = 0x124
ARM_SYSREG_R8_USR ArmSysreg = 0x125
ARM_SYSREG_R9_USR ArmSysreg = 0x126
ARM_SYSREG_R10_USR ArmSysreg = 0x127
ARM_SYSREG_R11_USR ArmSysreg = 0x128
ARM_SYSREG_R12_USR ArmSysreg = 0x129
ARM_SYSREG_SP_USR ArmSysreg = 0x12a
ARM_SYSREG_LR_USR ArmSysreg = 0x12b
ARM_SYSREG_R8_FIQ ArmSysreg = 0x12c
ARM_SYSREG_R9_FIQ ArmSysreg = 0x12d
ARM_SYSREG_R10_FIQ ArmSysreg = 0x12e
ARM_SYSREG_R11_FIQ ArmSysreg = 0x12f
ARM_SYSREG_R12_FIQ ArmSysreg = 0x130
ARM_SYSREG_SP_FIQ ArmSysreg = 0x131
ARM_SYSREG_LR_FIQ ArmSysreg = 0x132
ARM_SYSREG_LR_IRQ ArmSysreg = 0x133
ARM_SYSREG_SP_IRQ ArmSysreg = 0x134
ARM_SYSREG_LR_SVC ArmSysreg = 0x135
ARM_SYSREG_SP_SVC ArmSysreg = 0x136
ARM_SYSREG_LR_ABT ArmSysreg = 0x137
ARM_SYSREG_SP_ABT ArmSysreg = 0x138
ARM_SYSREG_LR_UND ArmSysreg = 0x139
ARM_SYSREG_SP_UND ArmSysreg = 0x13a
ARM_SYSREG_LR_MON ArmSysreg = 0x13b
ARM_SYSREG_SP_MON ArmSysreg = 0x13c
ARM_SYSREG_ELR_HYP ArmSysreg = 0x13d
ARM_SYSREG_SP_HYP ArmSysreg = 0x13e
ARM_SYSREG_SPSR_FIQ ArmSysreg = 0x13f
ARM_SYSREG_SPSR_IRQ ArmSysreg = 0x140
ARM_SYSREG_SPSR_SVC ArmSysreg = 0x141
ARM_SYSREG_SPSR_ABT ArmSysreg = 0x142
ARM_SYSREG_SPSR_UND ArmSysreg = 0x143
ARM_SYSREG_SPSR_MON ArmSysreg = 0x144
ARM_SYSREG_SPSR_HYP ArmSysreg = 0x145
)
type ArmVectordataType uint32
const (
ARM_VECTORDATA_INVALID ArmVectordataType = 0x0
ARM_VECTORDATA_I8 ArmVectordataType = 0x1
ARM_VECTORDATA_I16 ArmVectordataType = 0x2
ARM_VECTORDATA_I32 ArmVectordataType = 0x3
ARM_VECTORDATA_I64 ArmVectordataType = 0x4
ARM_VECTORDATA_S8 ArmVectordataType = 0x5
ARM_VECTORDATA_S16 ArmVectordataType = 0x6
ARM_VECTORDATA_S32 ArmVectordataType = 0x7
ARM_VECTORDATA_S64 ArmVectordataType = 0x8
ARM_VECTORDATA_U8 ArmVectordataType = 0x9
ARM_VECTORDATA_U16 ArmVectordataType = 0xa
ARM_VECTORDATA_U32 ArmVectordataType = 0xb
ARM_VECTORDATA_U64 ArmVectordataType = 0xc
ARM_VECTORDATA_P8 ArmVectordataType = 0xd
ARM_VECTORDATA_F16 ArmVectordataType = 0xe
ARM_VECTORDATA_F32 ArmVectordataType = 0xf
ARM_VECTORDATA_F64 ArmVectordataType = 0x10
ARM_VECTORDATA_F16F64 ArmVectordataType = 0x11
ARM_VECTORDATA_F64F16 ArmVectordataType = 0x12
ARM_VECTORDATA_F32F16 ArmVectordataType = 0x13
ARM_VECTORDATA_F16F32 ArmVectordataType = 0x14
ARM_VECTORDATA_F64F32 ArmVectordataType = 0x15
ARM_VECTORDATA_F32F64 ArmVectordataType = 0x16
ARM_VECTORDATA_S32F32 ArmVectordataType = 0x17
ARM_VECTORDATA_U32F32 ArmVectordataType = 0x18
ARM_VECTORDATA_F32S32 ArmVectordataType = 0x19
ARM_VECTORDATA_F32U32 ArmVectordataType = 0x1a
ARM_VECTORDATA_F64S16 ArmVectordataType = 0x1b
ARM_VECTORDATA_F32S16 ArmVectordataType = 0x1c
ARM_VECTORDATA_F64S32 ArmVectordataType = 0x1d
ARM_VECTORDATA_S16F64 ArmVectordataType = 0x1e
ARM_VECTORDATA_S16F32 ArmVectordataType = 0x1f
ARM_VECTORDATA_S32F64 ArmVectordataType = 0x20
ARM_VECTORDATA_U16F64 ArmVectordataType = 0x21
ARM_VECTORDATA_U16F32 ArmVectordataType = 0x22
ARM_VECTORDATA_U32F64 ArmVectordataType = 0x23
ARM_VECTORDATA_F64U16 ArmVectordataType = 0x24
ARM_VECTORDATA_F32U16 ArmVectordataType = 0x25
ARM_VECTORDATA_F64U32 ArmVectordataType = 0x26
ARM_VECTORDATA_F16U16 ArmVectordataType = 0x27
ARM_VECTORDATA_U16F16 ArmVectordataType = 0x28
ARM_VECTORDATA_F16U32 ArmVectordataType = 0x29
ARM_VECTORDATA_U32F16 ArmVectordataType = 0x2a
)
type ArmOpMem struct {
Base uint32
Index uint32
Scale int32
Disp int32
Lshift int32
}
type CsArm struct {
Usermode bool
Vector_size int32
Vector_data uint32
Cps_mode uint32
Cps_flag uint32
Cc uint32
Update_flags bool
Writeback bool
Mem_barrier uint32
Op_count uint8
_ [4]byte
Operands [36]CsArm64Op
}
type CsArmOp struct {
Vector_index int32
Shift CsShift
Type uint32
Reg int32
Imm int32
Fp float64
Mem ArmOpMem
Setend uint32
Subtracted bool
Access uint8
Neon_lane int8
_ [5]byte
}