diff --git a/lib/Transforms/YosysOptimizer/BooleanGateImporter.cpp b/lib/Transforms/YosysOptimizer/BooleanGateImporter.cpp index 6d2613645..8489a80f3 100644 --- a/lib/Transforms/YosysOptimizer/BooleanGateImporter.cpp +++ b/lib/Transforms/YosysOptimizer/BooleanGateImporter.cpp @@ -20,14 +20,16 @@ namespace heir { mlir::Operation *BooleanGateImporter::createOp(Yosys::RTLIL::Cell *cell, SmallVector &inputs, ImplicitLocOpBuilder &b) const { - auto op = llvm::StringSwitch(cell->type.substr(1)) - .Case("inv", b.create(inputs[0], false)) - .Case("xnor2", b.create(inputs, false)) - .Case("and2", b.create(inputs, false)) - .Case("xor2", b.create(inputs, false)) - .Case("nand2", b.create(inputs, false)) - .Case("nor2", b.create(inputs, false)) - .Case("or2", b.create(inputs, false)) + // standard cell names look like $_CELL_ + auto op = llvm::StringSwitch( + cell->type.substr(2, cell->type.size() - 3)) + .Case("NOT", b.create(inputs[0], false)) + .Case("XNOR", b.create(inputs, false)) + .Case("AND", b.create(inputs, false)) + .Case("XOR", b.create(inputs, false)) + .Case("NAND", b.create(inputs, false)) + .Case("NOR", b.create(inputs, false)) + .Case("OR", b.create(inputs, false)) .Default(nullptr); if (op == nullptr) { llvm_unreachable("unexpected cell type"); diff --git a/lib/Transforms/YosysOptimizer/YosysOptimizer.cpp b/lib/Transforms/YosysOptimizer/YosysOptimizer.cpp index f81a31a80..757895b63 100644 --- a/lib/Transforms/YosysOptimizer/YosysOptimizer.cpp +++ b/lib/Transforms/YosysOptimizer/YosysOptimizer.cpp @@ -87,13 +87,12 @@ stat; // $2: abc path // $3: yosys runfiles path // $4: abc fast option -fast -// TODO(#554): Re-enable -fast mode. constexpr std::string_view kYosysBooleanTemplate = R"( read_verilog {0}; hierarchy -check -top \{1}; proc; memory; stat; techmap -map {3}/techmap.v; opt; stat; -abc -exe {2} -liberty {3}/tfhe-rs_cells.liberty; stat; +abc -exe {2} -g AND,NAND,OR,NOR,XOR,XNOR {4}; opt_clean -purge; stat; rename -hide */c:*; rename -enumerate */c:*; hierarchy -generate * o:Y i:*; opt; opt_clean -purge; diff --git a/lib/Transforms/YosysOptimizer/yosys/BUILD b/lib/Transforms/YosysOptimizer/yosys/BUILD index f12d811d9..e89c5930c 100644 --- a/lib/Transforms/YosysOptimizer/yosys/BUILD +++ b/lib/Transforms/YosysOptimizer/yosys/BUILD @@ -9,6 +9,5 @@ filegroup( name = "share_files", srcs = glob([ "*.v", - "*.liberty", ]), ) diff --git a/lib/Transforms/YosysOptimizer/yosys/tfhe-rs_cells.liberty b/lib/Transforms/YosysOptimizer/yosys/tfhe-rs_cells.liberty deleted file mode 100644 index 4fa43fca3..000000000 --- a/lib/Transforms/YosysOptimizer/yosys/tfhe-rs_cells.liberty +++ /dev/null @@ -1,260 +0,0 @@ -/********************************************/ -/* */ -/* Supergate cell library for Bench marking */ -/* */ -/* Symbiotic EDA GmbH / Moseley Instruments */ -/* Niels A. Moseley */ -/* */ -/* Process: none */ -/* */ -/* Date : 02-11-2018 */ -/* Version: 1.0 */ -/* */ -/********************************************/ - -library(supergate) { - delay_model : table_lookup; - time_unit : "1ns"; - - /* Inverter */ - cell(inv) { - area : 0; - pin(A) { - direction : input; - } - - pin(Y) { - direction : output; - function : "A'"; - timing() { - related_pin : "A"; - timing_sense : negative_unate; - cell_rise(scalar) { - values("0.0"); - } - cell_fall(scalar) { - values("0.0"); - } - rise_transition(scalar) { - values("0.0"); - } - fall_transition(scalar) { - values("0.0"); - } - } - } - } - - cell(buffer) { - area : 0; - pin(A) { - direction : input; - } - pin(Y) { - direction : output; - function : "A"; - timing() { - related_pin : "A"; - timing_sense : positive_unate; - cell_rise(scalar) { - values("0.0"); - } - cell_fall(scalar) { - values("0.0"); - } - rise_transition(scalar) { - values("0.0"); - } - fall_transition(scalar) { - values("0.0"); - } - } - } - } - - /* 2-input AND gate */ - cell(and2) { - area : 100; - pin(A) { - direction : input; - } - pin(B) { - direction : input; - } - pin(Y) { - direction: output; - function : "(A * B)"; - timing() { - related_pin : "A B"; - timing_sense : positive_unate; - cell_rise(scalar) { - values("1000.0"); - } - cell_fall(scalar) { - values("1000.0"); - } - rise_transition(scalar) { - values("1000.0"); - } - fall_transition(scalar) { - values("1000.0"); - } - } - } - } - - /* 2-input NAND gate */ - cell(nand2) { - area : 100; - pin(A) { - direction : input; - } - pin(B) { - direction : input; - } - pin(Y) { - direction: output; - function : "(A * B)'"; - timing() { - related_pin : "A B"; - timing_sense : negative_unate; - cell_rise(scalar) { - values("1000.0"); - } - cell_fall(scalar) { - values("1000.0"); - } - rise_transition(scalar) { - values("1000.0"); - } - fall_transition(scalar) { - values("1000.0"); - } - } - } - } - - /* 2-input OR gate */ - cell(or2) { - area : 100; - pin(A) { - direction : input; - } - pin(B) { - direction : input; - } - pin(Y) { - direction: output; - function : "(A + B)"; - timing() { - related_pin : "A B"; - timing_sense : positive_unate; - cell_rise(scalar) { - values("1000.0"); - } - cell_fall(scalar) { - values("1000.0"); - } - rise_transition(scalar) { - values("1000.0"); - } - fall_transition(scalar) { - values("1000.0"); - } - } - } - } - - /* 2-input NOR gate */ - cell(nor2) { - area : 100; - pin(A) { - direction : input; - } - pin(B) { - direction : input; - } - pin(Y) { - direction: output; - function : "(A + B)'"; - timing() { - related_pin : "A B"; - timing_sense : negative_unate; - cell_rise(scalar) { - values("1000.0"); - } - cell_fall(scalar) { - values("1000.0"); - } - rise_transition(scalar) { - values("1000.0"); - } - fall_transition(scalar) { - values("1000.0"); - } - } - } - } - - /* 2-input XOR */ - cell(xor2) { - area : 100; - pin(A) { - direction : input; - } - pin(B) { - direction : input; - } - pin(Y) { - direction: output; - function : "(A * (B')) + ((A') * B)"; - timing() { - related_pin : "A B"; - timing_sense : non_unate; - cell_rise(scalar) { - values("1000.0"); - } - cell_fall(scalar) { - values("1000.0"); - } - rise_transition(scalar) { - values("1000.0"); - } - fall_transition(scalar) { - values("1000.0"); - } - } - } - } - - /* 2-input XNOR */ - cell(xnor2) { - area : 100; - pin(A) { - direction : input; - } - pin(B) { - direction : input; - } - pin(Y) { - direction: output; - function : "((A * (B')) + ((A') * B))'"; - timing() { - related_pin : "A B"; - timing_sense : non_unate; - cell_rise(scalar) { - values("1000.0"); - } - cell_fall(scalar) { - values("1000.0"); - } - rise_transition(scalar) { - values("1000.0"); - } - fall_transition(scalar) { - values("1000.0"); - } - } - } - } -} /* end */ diff --git a/tests/yosys_optimizer/add_one.mlir b/tests/yosys_optimizer/add_one.mlir index cd0cf3522..2618b25ce 100644 --- a/tests/yosys_optimizer/add_one.mlir +++ b/tests/yosys_optimizer/add_one.mlir @@ -1,5 +1,7 @@ -// RUN: heir-opt --yosys-optimizer --canonicalize --cse %s | FileCheck %s +// RUN: heir-opt --yosys-optimizer --canonicalize --cse %s | FileCheck %s --check-prefix=CHECK --check-prefix=LUT +// RUN: heir-opt --yosys-optimizer="abc-fast=True" --canonicalize --cse %s | FileCheck %s --check-prefix=CHECK --check-prefix=LUT-FAST // RUN: heir-opt --yosys-optimizer="mode=Boolean" --canonicalize --cse %s | FileCheck --check-prefix=CHECK --check-prefix=BOOL %s +// RUN: heir-opt --yosys-optimizer="mode=Boolean abc-fast=True" --canonicalize --cse %s | FileCheck --check-prefix=CHECK --check-prefix=BOOL-FAST %s module { // CHECK-LABEL: @add_one @@ -14,7 +16,16 @@ module { ins(%in, %one: !secret.secret, i8) { ^bb0(%IN: i8, %ONE: i8) : // CHECK-NOT: arith.addi - // BOOL-COUNT-7: comb.inv + + // LUT-COUNT-11: comb.truth_table + // LUT-FAST-COUNT-13: comb.truth_table + // BOOL-COUNT-14: comb + // BOOL-FAST-COUNT-16: comb + + // LUT-NOT: comb.truth_table + // LUT-FAST-NOT: comb.truth_table + // BOOL-NOT: comb + // BOOL-FAST-NOT: comb %2 = arith.addi %IN, %ONE : i8 secret.yield %2 : i8 } -> (!secret.secret)