Add Google's Verible verilog formatter for verilog, systemverilog files

[snsokolov]

Verible formatter is located here http://github.com/google/verible.

@fangism

[fangism]

@hzeller @msfschaffner This might be an alternative way to support formatting for your project environment.

[msfschaffner]

Interesting, thanks for the pointer @fangism !

@eunchan for visibility

[hzeller]

Related request in verible: chipsalliance/verible#192

[snsokolov]

Update: I had some pieces of the support ready in the internal CL, and I was asked by the project maintainers to contribute to this open sourced repository instead (which is great).

I'll convert my changes into a PR in the next few days.