Got this error while running symbolator on a verilog file #12
Comments
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I know with VHDL, the component needs to be within a package for it to work, and I'm not sure what the verilog equivalent is. If you're using the fork I made though, I'm still trying to figure out how everything works and could have messed it up. I need to do more tests on verilog code |
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how does this verilog file look like? does it use c-style ports? does it use any SV (maybe interfaces?) feature? can you post it here? (at least the module declaration) |
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sure. Here is the complete file. It instantiates one module which is a shift register. I don't think it has anything out of the ordinary `timescale 1ns / 1ps
module alu #(parameter bit_width = 8,parameter ip_size = 16, parameter window_size = 3)(
input clk,
input rst,
input clk_en,
input [bit_width-1:0] data,
input wire [71:0] weight_array,
output wire [17:0] sum_out
);
wire [16:0] sum;
wire [7:0] weights [0:8];
wire [bit_width*(ip_size+2)-1:0] reg1_op,reg2_op;
wire [bit_width*window_size-1:0] reg3_op;
reg [15:0] product [0:8];
reg ce;
generate
genvar unpk_idx;
for (unpk_idx=0; unpk_idx<(9); unpk_idx=unpk_idx+1)
begin:unpack1
assign weights[unpk_idx][7:0] = weight_array[((8)*unpk_idx) +: 8];
end
endgenerate
variable_shift_reg #(bit_width,ip_size+2) s1 (clk,ce,rst,data,reg1_op);
variable_shift_reg #(bit_width,ip_size+2) s2 (clk,ce,rst,reg1_op[bit_width*(ip_size+2)-1:bit_width*(ip_size+1)],reg2_op);
variable_shift_reg #(bit_width,window_size) s3 (clk,ce,rst,reg2_op[bit_width*(ip_size+2)-1:bit_width*(ip_size+1)],reg3_op);
always@(posedge clk) begin
ce <= clk_en;
end
generate
genvar i;
for(i=0;i<9;i=i+1)
begin:block2
always@(posedge clk or posedge rst) begin
if(rst)
begin
product[i] <= 16'b0;
end
else
if(ce)
begin
if(i <= 2)
begin
product[i] <= weights[i] * reg1_op[bit_width*(i+1)-1:bit_width*i];
end
else if(i > 2 && i <= 5)
begin
product[i] <= weights[i] * reg2_op[bit_width*(i-3+1)-1:bit_width*(i-3)];
end
else if(i > 5)
begin
product[i] <= weights[i] * reg3_op[bit_width*(i-6+1)-1:bit_width*(i-6)];
end
end
end
end
endgenerate
assign sum_out = product[0]+product[1]+product[2]+product[3]+product[4]+product[5]+product[6]+product[7]+product[8];
endmodule |
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What version of symbolator are you using? It worked for me using my (hopefully temporary) fork and the version currently available in pip. I am using python3 which may be the difference though.
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Just updated my files from your fork and tried again. Still no luck. The symbolator I downloaded from pip3 has a version |
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@nobodywasishere If you don't mind could you please tell me the versions of hdlparse, pycairo and pygobject that you have? |
I want to test this in a fresh Ubuntu VM to see if I can reproduce the error. What version of Ubuntu are you using? Also, my fork should have version 1.0.2a to differentiate between them. |
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@nobodywasishere I updated my packages (pygobject,hdlparse) to the versions in your system and it is now working. |
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FYI - We have started maintaining a symbolator fork in the SymbiFlow organization (https://github.com/SymbiFlow/symbolator). We are reviewing and accepting pull requests as the tool is being heavily used in SymbiFlow and Google's skywater-pdk documentation. At some point we might rename it to something like symbiflow-symbolator and publish it on PyPi and similar. |
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My fork is a move to only Python 3, fixes for some bugs I ran into, and a merge of the changes made by various forks of the original repo. It was more of a short-term test than a long-term maintain. If we can get this updated and rolling again, I'd be more than happy to help. I would also fork hdlparse if possible so we can get that rolling too. Stuff like parsing VHDL entities instead of just packages requires changing hdlparse, and there's already code for both in adding this feature waiting to be merged. |
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We are mainly using symbolator with verilog and don't have a huge interest in VHDL (but perfectly happy for other people to work on that). |
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@mithro what exactly are you planning with Symbolator in the Symbiflow project? I think Its high time someone created an open-source HDL to block diagram converter that enables easier design exploration by allowing us to zoom into the sub-modules without having to synthesize the design. Something like the Schematic Viewer in Vivado and ISE except much lighter and faster. If something like that is on the charts. I would love to contribute to the project. |
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@sumanth-kalluri - Don't have any plans to dramatically improve things in symbolator, we just need basic block diagrams for things like the skywater-pdk. There are other projects working on the schematic viewer idea -- see f4pga/ideas#41 -- I actually think there is a GSoC project related to that... |
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@mithro I wish I was still a student. Anyways great to see such interest being taken on this idea. |
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@mithro What are your plans in terms of Python 2 support since Python 2.7 is now EOL? I can do a PR for my changes to Python 3 only on your fork if you want. |
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I think supporting Python 3 is important. |
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@sumanth-kalluri -- There was also a discussion about this topic at https://groups.google.com/forum/#!msg/eda-playground/Mh9bOhC7FNQ/w7GKEEqlAAAJ and potential of using Surelog to do this -> https://github.com/alainmarcel/Surelog |
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I went through and redid my forks of symbolator and hdlparse in a cleaner fashion. Each has an entity branch specifically for entity support and I updated the version numbers for those branches as to prevent compatibility errors when installing (you'd need to install both entity branches manually for VHDL entities to work). I pulled in all the various changes people have made on their own forks as well. I'll probably maintain these just for personal use. I also made a PR to SymbiFlow/symbolator with the changes I specifically made to drop Python 2.7 and fix a PyGIWarning. I hope that works for what you're looking for. |
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Thank you guys and thanks @nobodywasishere , this is excellent work |
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@nobodywasishere Your entity branches worked great for what I am doing. I'll try to keep up to date with the development happening here and contribute to the Symbiflow fork. |
Is symbolator properly supported for verilog? I got the following error when I ran it on a .v file. I have tried out multiple output formats etc. but no joy.
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