Verilog unpacked arrays not supported

[ghost]

Hi Kevin,

I have this module

module abc (
input clk;
input rst;
input [7:0] data[4];
output [7:0]
);
// Missing code doesn't change symbolator behaviour
endmodule

Symbolator generates this:

So there seems to be a problem with unpacked arrays.

Best wishes and keep on rockin'!