Disconnecting LiteDRAM and using interface for MIG / Other RAM Interfacing

[Beauxrel]

I am trying to replace the LiteDRAM core with MIG, I have a design that already integrates the Xilinx MIG and would like my soc to share the DRAM with that system so that I can read data into my litex soc and process it.

This is what I imagine the architecture should look like.

From This Post

I made these changes, but I don't think this accounts for the CPU being connected to LiteDRAM, that happens above this.

            #Wishbone Slave <--> LiteDRAM bridge.
            #self.wishbone_bridge = LiteDRAMWishbone2Native(
            #    wishbone     = litedram_wb,
            #    port         = port,
            #    base_address = self.bus.regions["main_ram"].origin
            # )

                     #-------------------AXI INTERFACE DEVELOPMENT-------------
            # Wishbone Slave <--> LiteDRAM bridge.
            from litex.build.generic_platform import Subsignal, Pins
            from litex.soc.interconnect.axi import Wishbone2AXI
            from litex.soc.interconnect.axi import Wishbone2AXILite
            from litex.soc.interconnect.axi import AXIDownConverter
            from litex.soc.interconnect.axi import AXI2Wishbone
            from litex.soc.interconnect.axi import AXIInterface
            from litex.soc.interconnect.axi import AXILiteInterface
            from litedram.frontend.axi import LiteDRAMAXIPort
            from litex_boards.platforms import xilinx_vcu108

            data_width = 512
            address_width = 31
            landon_wb_port = wishbone.Interface(data_width=data_width,adr_width=25)
            wishbone.Converter(litedram_wb,landon_wb_port)
            landon_axi_port = axi.AXIInterface(data_width=data_width, address_width=address_width)
            landon_axil_port = AXILiteInterface(data_width=data_width,address_width=address_width)
            axi_sdram = Wishbone2AXILite(landon_wb_port,landon_axil_port)
            self.submodules += axi.AXILite2AXI(landon_axil_port,landon_axi_port)

I also tried to rip out add_sdram and just paste it into my targets file.

        self.cpu.add_memory_buses(
        address_width = 32,
        data_width    = 512
        )



        main_ram_region = SoCRegion(
        origin = 0x40000000,
        size   = 0x40000000,
        mode   = "rwx")
        self.bus.add_region("main_ram", main_ram_region)
        
        

        data_width = 512
        address_width = 31
        wb_sdram = wishbone.Interface(data_width=self.bus.data_width)
        self.bus.add_slave("main_ram", wb_sdram)
        landon_wb_port = wishbone.Interface(data_width=data_width,adr_width=25)
        wishbone.Converter(wb_sdram,landon_wb_port)
        landon_axi_port = axi.AXIInterface(data_width=data_width, address_width=address_width)
        landon_axil_port = AXILiteInterface(data_width=data_width,address_width=address_width)
        axi_sdram = Wishbone2AXILite(landon_wb_port,landon_axil_port,base_address=self.bus.regions["main_ram"].origin)
        self.submodules += axi.AXILite2AXI(landon_axil_port,landon_axi_port)

Please help me.