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disasm-ia32.cc
2799 lines (2651 loc) · 90.5 KB
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disasm-ia32.cc
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// Copyright 2011 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include <assert.h>
#include <stdarg.h>
#include <stdio.h>
#if V8_TARGET_ARCH_IA32
#include "src/base/compiler-specific.h"
#include "src/codegen/ia32/sse-instr.h"
#include "src/diagnostics/disasm.h"
#include "src/utils/utils.h"
namespace disasm {
enum OperandOrder { UNSET_OP_ORDER = 0, REG_OPER_OP_ORDER, OPER_REG_OP_ORDER };
//------------------------------------------------------------------
// Tables
//------------------------------------------------------------------
struct ByteMnemonic {
int b; // -1 terminates, otherwise must be in range (0..255)
const char* mnem;
OperandOrder op_order_;
};
static const ByteMnemonic two_operands_instr[] = {
{0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER},
{0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER},
{0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER},
{0x21, "and", OPER_REG_OP_ORDER}, {0x23, "and", REG_OPER_OP_ORDER},
{0x29, "sub", OPER_REG_OP_ORDER}, {0x2A, "subb", REG_OPER_OP_ORDER},
{0x2B, "sub", REG_OPER_OP_ORDER}, {0x31, "xor", OPER_REG_OP_ORDER},
{0x33, "xor", REG_OPER_OP_ORDER}, {0x38, "cmpb", OPER_REG_OP_ORDER},
{0x39, "cmp", OPER_REG_OP_ORDER}, {0x3A, "cmpb", REG_OPER_OP_ORDER},
{0x3B, "cmp", REG_OPER_OP_ORDER}, {0x84, "test_b", REG_OPER_OP_ORDER},
{0x85, "test", REG_OPER_OP_ORDER}, {0x86, "xchg_b", REG_OPER_OP_ORDER},
{0x87, "xchg", REG_OPER_OP_ORDER}, {0x8A, "mov_b", REG_OPER_OP_ORDER},
{0x8B, "mov", REG_OPER_OP_ORDER}, {0x8D, "lea", REG_OPER_OP_ORDER},
{-1, "", UNSET_OP_ORDER}};
static const ByteMnemonic zero_operands_instr[] = {
{0xC3, "ret", UNSET_OP_ORDER}, {0xC9, "leave", UNSET_OP_ORDER},
{0x90, "nop", UNSET_OP_ORDER}, {0xF4, "hlt", UNSET_OP_ORDER},
{0xCC, "int3", UNSET_OP_ORDER}, {0x60, "pushad", UNSET_OP_ORDER},
{0x61, "popad", UNSET_OP_ORDER}, {0x9C, "pushfd", UNSET_OP_ORDER},
{0x9D, "popfd", UNSET_OP_ORDER}, {0x9E, "sahf", UNSET_OP_ORDER},
{0x99, "cdq", UNSET_OP_ORDER}, {0x9B, "fwait", UNSET_OP_ORDER},
{0xFC, "cld", UNSET_OP_ORDER}, {0xAB, "stos", UNSET_OP_ORDER},
{-1, "", UNSET_OP_ORDER}};
static const ByteMnemonic call_jump_instr[] = {{0xE8, "call", UNSET_OP_ORDER},
{0xE9, "jmp", UNSET_OP_ORDER},
{-1, "", UNSET_OP_ORDER}};
static const ByteMnemonic short_immediate_instr[] = {
{0x05, "add", UNSET_OP_ORDER}, {0x0D, "or", UNSET_OP_ORDER},
{0x15, "adc", UNSET_OP_ORDER}, {0x25, "and", UNSET_OP_ORDER},
{0x2D, "sub", UNSET_OP_ORDER}, {0x35, "xor", UNSET_OP_ORDER},
{0x3D, "cmp", UNSET_OP_ORDER}, {-1, "", UNSET_OP_ORDER}};
// Generally we don't want to generate these because they are subject to partial
// register stalls. They are included for completeness and because the cmp
// variant is used by the RecordWrite stub. Because it does not update the
// register it is not subject to partial register stalls.
static ByteMnemonic byte_immediate_instr[] = {{0x0C, "or", UNSET_OP_ORDER},
{0x24, "and", UNSET_OP_ORDER},
{0x34, "xor", UNSET_OP_ORDER},
{0x3C, "cmp", UNSET_OP_ORDER},
{-1, "", UNSET_OP_ORDER}};
static const char* const jump_conditional_mnem[] = {
/*0*/ "jo", "jno", "jc", "jnc",
/*4*/ "jz", "jnz", "jna", "ja",
/*8*/ "js", "jns", "jpe", "jpo",
/*12*/ "jl", "jnl", "jng", "jg"};
static const char* const set_conditional_mnem[] = {
/*0*/ "seto", "setno", "setc", "setnc",
/*4*/ "setz", "setnz", "setna", "seta",
/*8*/ "sets", "setns", "setpe", "setpo",
/*12*/ "setl", "setnl", "setng", "setg"};
static const char* const conditional_move_mnem[] = {
/*0*/ "cmovo", "cmovno", "cmovc", "cmovnc",
/*4*/ "cmovz", "cmovnz", "cmovna", "cmova",
/*8*/ "cmovs", "cmovns", "cmovpe", "cmovpo",
/*12*/ "cmovl", "cmovnl", "cmovng", "cmovg"};
enum InstructionType {
NO_INSTR,
ZERO_OPERANDS_INSTR,
TWO_OPERANDS_INSTR,
JUMP_CONDITIONAL_SHORT_INSTR,
REGISTER_INSTR,
MOVE_REG_INSTR,
CALL_JUMP_INSTR,
SHORT_IMMEDIATE_INSTR,
BYTE_IMMEDIATE_INSTR
};
struct InstructionDesc {
const char* mnem;
InstructionType type;
OperandOrder op_order_;
};
class InstructionTable {
public:
InstructionTable();
const InstructionDesc& Get(byte x) const { return instructions_[x]; }
static InstructionTable* get_instance() {
static InstructionTable table;
return &table;
}
private:
InstructionDesc instructions_[256];
void Clear();
void Init();
void CopyTable(const ByteMnemonic bm[], InstructionType type);
void SetTableRange(InstructionType type, byte start, byte end,
const char* mnem);
void AddJumpConditionalShort();
};
InstructionTable::InstructionTable() {
Clear();
Init();
}
void InstructionTable::Clear() {
for (int i = 0; i < 256; i++) {
instructions_[i].mnem = "";
instructions_[i].type = NO_INSTR;
instructions_[i].op_order_ = UNSET_OP_ORDER;
}
}
void InstructionTable::Init() {
CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
CopyTable(call_jump_instr, CALL_JUMP_INSTR);
CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
CopyTable(byte_immediate_instr, BYTE_IMMEDIATE_INSTR);
AddJumpConditionalShort();
SetTableRange(REGISTER_INSTR, 0x40, 0x47, "inc");
SetTableRange(REGISTER_INSTR, 0x48, 0x4F, "dec");
SetTableRange(REGISTER_INSTR, 0x50, 0x57, "push");
SetTableRange(REGISTER_INSTR, 0x58, 0x5F, "pop");
SetTableRange(REGISTER_INSTR, 0x91, 0x97, "xchg eax,"); // 0x90 is nop.
SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, "mov");
}
void InstructionTable::CopyTable(const ByteMnemonic bm[],
InstructionType type) {
for (int i = 0; bm[i].b >= 0; i++) {
InstructionDesc* id = &instructions_[bm[i].b];
id->mnem = bm[i].mnem;
id->op_order_ = bm[i].op_order_;
DCHECK_EQ(NO_INSTR, id->type); // Information not already entered.
id->type = type;
}
}
void InstructionTable::SetTableRange(InstructionType type, byte start, byte end,
const char* mnem) {
for (byte b = start; b <= end; b++) {
InstructionDesc* id = &instructions_[b];
DCHECK_EQ(NO_INSTR, id->type); // Information not already entered.
id->mnem = mnem;
id->type = type;
}
}
void InstructionTable::AddJumpConditionalShort() {
for (byte b = 0x70; b <= 0x7F; b++) {
InstructionDesc* id = &instructions_[b];
DCHECK_EQ(NO_INSTR, id->type); // Information not already entered.
id->mnem = jump_conditional_mnem[b & 0x0F];
id->type = JUMP_CONDITIONAL_SHORT_INSTR;
}
}
namespace {
int8_t Imm8(const uint8_t* data) {
return *reinterpret_cast<const int8_t*>(data);
}
uint8_t Imm8_U(const uint8_t* data) {
return *reinterpret_cast<const uint8_t*>(data);
}
int16_t Imm16(const uint8_t* data) {
return *reinterpret_cast<const int16_t*>(data);
}
uint16_t Imm16_U(const uint8_t* data) {
return *reinterpret_cast<const uint16_t*>(data);
}
int32_t Imm32(const uint8_t* data) {
return *reinterpret_cast<const int32_t*>(data);
}
} // namespace
// The IA32 disassembler implementation.
class DisassemblerIA32 {
public:
DisassemblerIA32(
const NameConverter& converter,
Disassembler::UnimplementedOpcodeAction unimplemented_opcode_action)
: converter_(converter),
vex_byte0_(0),
vex_byte1_(0),
vex_byte2_(0),
instruction_table_(InstructionTable::get_instance()),
tmp_buffer_pos_(0),
unimplemented_opcode_action_(unimplemented_opcode_action) {
tmp_buffer_[0] = '\0';
}
virtual ~DisassemblerIA32() {}
// Writes one disassembled instruction into 'buffer' (0-terminated).
// Returns the length of the disassembled machine instruction in bytes.
int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
private:
const NameConverter& converter_;
byte vex_byte0_; // 0xC4 or 0xC5
byte vex_byte1_;
byte vex_byte2_; // only for 3 bytes vex prefix
InstructionTable* instruction_table_;
v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
unsigned int tmp_buffer_pos_;
Disassembler::UnimplementedOpcodeAction unimplemented_opcode_action_;
enum {
eax = 0,
ecx = 1,
edx = 2,
ebx = 3,
esp = 4,
ebp = 5,
esi = 6,
edi = 7
};
enum ShiftOpcodeExtension {
kROL = 0,
kROR = 1,
kRCL = 2,
kRCR = 3,
kSHL = 4,
KSHR = 5,
kSAR = 7
};
bool vex_128() {
DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
return (checked & 4) == 0;
}
bool vex_none() {
DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
return (checked & 3) == 0;
}
bool vex_66() {
DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
return (checked & 3) == 1;
}
bool vex_f3() {
DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
return (checked & 3) == 2;
}
bool vex_f2() {
DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
return (checked & 3) == 3;
}
bool vex_w() {
if (vex_byte0_ == 0xC5) return false;
return (vex_byte2_ & 0x80) != 0;
}
bool vex_0f() {
if (vex_byte0_ == 0xC5) return true;
return (vex_byte1_ & 3) == 1;
}
bool vex_0f38() {
if (vex_byte0_ == 0xC5) return false;
return (vex_byte1_ & 3) == 2;
}
bool vex_0f3a() {
if (vex_byte0_ == 0xC5) return false;
return (vex_byte1_ & 3) == 3;
}
int vex_vreg() {
DCHECK(vex_byte0_ == 0xC4 || vex_byte0_ == 0xC5);
byte checked = vex_byte0_ == 0xC4 ? vex_byte2_ : vex_byte1_;
return ~(checked >> 3) & 0xF;
}
char float_size_code() { return "sd"[vex_w()]; }
const char* NameOfCPURegister(int reg) const {
return converter_.NameOfCPURegister(reg);
}
const char* NameOfByteCPURegister(int reg) const {
return converter_.NameOfByteCPURegister(reg);
}
const char* NameOfXMMRegister(int reg) const {
return converter_.NameOfXMMRegister(reg);
}
const char* NameOfAddress(byte* addr) const {
return converter_.NameOfAddress(addr);
}
// Disassembler helper functions.
static void get_modrm(byte data, int* mod, int* regop, int* rm) {
*mod = (data >> 6) & 3;
*regop = (data & 0x38) >> 3;
*rm = data & 7;
}
static void get_sib(byte data, int* scale, int* index, int* base) {
*scale = (data >> 6) & 3;
*index = (data >> 3) & 7;
*base = data & 7;
}
using RegisterNameMapping = const char* (DisassemblerIA32::*)(int reg) const;
int PrintRightOperandHelper(byte* modrmp, RegisterNameMapping register_name);
int PrintRightOperand(byte* modrmp);
int PrintRightByteOperand(byte* modrmp);
int PrintRightXMMOperand(byte* modrmp);
int PrintOperands(const char* mnem, OperandOrder op_order, byte* data);
int PrintImmediateOp(byte* data);
int F7Instruction(byte* data);
int D1D3C1Instruction(byte* data);
int JumpShort(byte* data);
int JumpConditional(byte* data, const char* comment);
int JumpConditionalShort(byte* data, const char* comment);
int SetCC(byte* data);
int CMov(byte* data);
int FPUInstruction(byte* data);
int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
int AVXInstruction(byte* data);
PRINTF_FORMAT(2, 3) void AppendToBuffer(const char* format, ...);
void UnimplementedInstruction() {
if (unimplemented_opcode_action_ ==
Disassembler::kAbortOnUnimplementedOpcode) {
FATAL("Unimplemented instruction in disassembler");
} else {
AppendToBuffer("'Unimplemented Instruction'");
}
}
};
void DisassemblerIA32::AppendToBuffer(const char* format, ...) {
v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
va_list args;
va_start(args, format);
int result = v8::internal::VSNPrintF(buf, format, args);
va_end(args);
tmp_buffer_pos_ += result;
}
int DisassemblerIA32::PrintRightOperandHelper(
byte* modrmp, RegisterNameMapping direct_register_name) {
int mod, regop, rm;
get_modrm(*modrmp, &mod, ®op, &rm);
RegisterNameMapping register_name =
(mod == 3) ? direct_register_name : &DisassemblerIA32::NameOfCPURegister;
switch (mod) {
case 0:
if (rm == ebp) {
AppendToBuffer("[0x%x]", Imm32(modrmp + 1));
return 5;
} else if (rm == esp) {
byte sib = *(modrmp + 1);
int scale, index, base;
get_sib(sib, &scale, &index, &base);
if (index == esp && base == esp && scale == 0 /*times_1*/) {
AppendToBuffer("[%s]", (this->*register_name)(rm));
return 2;
} else if (base == ebp) {
int32_t disp = Imm32(modrmp + 2);
AppendToBuffer("[%s*%d%s0x%x]", (this->*register_name)(index),
1 << scale, disp < 0 ? "-" : "+",
disp < 0 ? -disp : disp);
return 6;
} else if (index != esp && base != ebp) {
// [base+index*scale]
AppendToBuffer("[%s+%s*%d]", (this->*register_name)(base),
(this->*register_name)(index), 1 << scale);
return 2;
} else {
UnimplementedInstruction();
return 1;
}
} else {
AppendToBuffer("[%s]", (this->*register_name)(rm));
return 1;
}
break;
case 1: // fall through
case 2:
if (rm == esp) {
byte sib = *(modrmp + 1);
int scale, index, base;
get_sib(sib, &scale, &index, &base);
int disp = mod == 2 ? Imm32(modrmp + 2) : Imm8(modrmp + 2);
if (index == base && index == rm /*esp*/ && scale == 0 /*times_1*/) {
AppendToBuffer("[%s%s0x%x]", (this->*register_name)(rm),
disp < 0 ? "-" : "+", disp < 0 ? -disp : disp);
} else {
AppendToBuffer("[%s+%s*%d%s0x%x]", (this->*register_name)(base),
(this->*register_name)(index), 1 << scale,
disp < 0 ? "-" : "+", disp < 0 ? -disp : disp);
}
return mod == 2 ? 6 : 3;
} else {
// No sib.
int disp = mod == 2 ? Imm32(modrmp + 1) : Imm8(modrmp + 1);
AppendToBuffer("[%s%s0x%x]", (this->*register_name)(rm),
disp < 0 ? "-" : "+", disp < 0 ? -disp : disp);
return mod == 2 ? 5 : 2;
}
break;
case 3:
AppendToBuffer("%s", (this->*register_name)(rm));
return 1;
default:
UnimplementedInstruction();
return 1;
}
UNREACHABLE();
}
int DisassemblerIA32::PrintRightOperand(byte* modrmp) {
return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfCPURegister);
}
int DisassemblerIA32::PrintRightByteOperand(byte* modrmp) {
return PrintRightOperandHelper(modrmp,
&DisassemblerIA32::NameOfByteCPURegister);
}
int DisassemblerIA32::PrintRightXMMOperand(byte* modrmp) {
return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfXMMRegister);
}
// Returns number of bytes used including the current *data.
// Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
int DisassemblerIA32::PrintOperands(const char* mnem, OperandOrder op_order,
byte* data) {
byte modrm = *data;
int mod, regop, rm;
get_modrm(modrm, &mod, ®op, &rm);
int advance = 0;
switch (op_order) {
case REG_OPER_OP_ORDER: {
AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
advance = PrintRightOperand(data);
break;
}
case OPER_REG_OP_ORDER: {
AppendToBuffer("%s ", mnem);
advance = PrintRightOperand(data);
AppendToBuffer(",%s", NameOfCPURegister(regop));
break;
}
default:
UNREACHABLE();
}
return advance;
}
// Returns number of bytes used by machine instruction, including *data byte.
// Writes immediate instructions to 'tmp_buffer_'.
int DisassemblerIA32::PrintImmediateOp(byte* data) {
bool sign_extension_bit = (*data & 0x02) != 0;
byte modrm = *(data + 1);
int mod, regop, rm;
get_modrm(modrm, &mod, ®op, &rm);
const char* mnem = "Imm???";
switch (regop) {
case 0:
mnem = "add";
break;
case 1:
mnem = "or";
break;
case 2:
mnem = "adc";
break;
case 4:
mnem = "and";
break;
case 5:
mnem = "sub";
break;
case 6:
mnem = "xor";
break;
case 7:
mnem = "cmp";
break;
default:
UnimplementedInstruction();
}
AppendToBuffer("%s ", mnem);
int count = PrintRightOperand(data + 1);
if (sign_extension_bit) {
AppendToBuffer(",0x%x", *(data + 1 + count));
return 1 + count + 1 /*int8*/;
} else {
AppendToBuffer(",0x%x", Imm32(data + 1 + count));
return 1 + count + 4 /*int32_t*/;
}
}
// Returns number of bytes used, including *data.
int DisassemblerIA32::F7Instruction(byte* data) {
DCHECK_EQ(0xF7, *data);
byte modrm = *++data;
int mod, regop, rm;
get_modrm(modrm, &mod, ®op, &rm);
const char* mnem = nullptr;
switch (regop) {
case 0:
mnem = "test";
break;
case 2:
mnem = "not";
break;
case 3:
mnem = "neg";
break;
case 4:
mnem = "mul";
break;
case 5:
mnem = "imul";
break;
case 6:
mnem = "div";
break;
case 7:
mnem = "idiv";
break;
default:
UnimplementedInstruction();
}
AppendToBuffer("%s ", mnem);
int count = PrintRightOperand(data);
if (regop == 0) {
AppendToBuffer(",0x%x", Imm32(data + count));
count += 4;
}
return 1 + count;
}
int DisassemblerIA32::D1D3C1Instruction(byte* data) {
byte op = *data;
DCHECK(op == 0xD1 || op == 0xD3 || op == 0xC1);
byte modrm = *++data;
int mod, regop, rm;
get_modrm(modrm, &mod, ®op, &rm);
int imm8 = -1;
const char* mnem = nullptr;
switch (regop) {
case kROL:
mnem = "rol";
break;
case kROR:
mnem = "ror";
break;
case kRCL:
mnem = "rcl";
break;
case kRCR:
mnem = "rcr";
break;
case kSHL:
mnem = "shl";
break;
case KSHR:
mnem = "shr";
break;
case kSAR:
mnem = "sar";
break;
default:
UnimplementedInstruction();
}
AppendToBuffer("%s ", mnem);
int count = PrintRightOperand(data);
if (op == 0xD1) {
imm8 = 1;
} else if (op == 0xC1) {
imm8 = *(data + 1);
count++;
} else if (op == 0xD3) {
// Shift/rotate by cl.
}
if (imm8 >= 0) {
AppendToBuffer(",%d", imm8);
} else {
AppendToBuffer(",cl");
}
return 1 + count;
}
// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpShort(byte* data) {
DCHECK_EQ(0xEB, *data);
byte b = *(data + 1);
byte* dest = data + static_cast<int8_t>(b) + 2;
AppendToBuffer("jmp %s", NameOfAddress(dest));
return 2;
}
// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditional(byte* data, const char* comment) {
DCHECK_EQ(0x0F, *data);
byte cond = *(data + 1) & 0x0F;
byte* dest = data + Imm32(data + 2) + 6;
const char* mnem = jump_conditional_mnem[cond];
AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
if (comment != nullptr) {
AppendToBuffer(", %s", comment);
}
return 6; // includes 0x0F
}
// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditionalShort(byte* data, const char* comment) {
byte cond = *data & 0x0F;
byte b = *(data + 1);
byte* dest = data + static_cast<int8_t>(b) + 2;
const char* mnem = jump_conditional_mnem[cond];
AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
if (comment != nullptr) {
AppendToBuffer(", %s", comment);
}
return 2;
}
// Returns number of bytes used, including *data.
int DisassemblerIA32::SetCC(byte* data) {
DCHECK_EQ(0x0F, *data);
byte cond = *(data + 1) & 0x0F;
const char* mnem = set_conditional_mnem[cond];
AppendToBuffer("%s ", mnem);
PrintRightByteOperand(data + 2);
return 3; // Includes 0x0F.
}
// Returns number of bytes used, including *data.
int DisassemblerIA32::CMov(byte* data) {
DCHECK_EQ(0x0F, *data);
byte cond = *(data + 1) & 0x0F;
const char* mnem = conditional_move_mnem[cond];
int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2);
return 2 + op_size; // includes 0x0F
}
const char* sf_str[4] = {"", "rl", "ra", "ll"};
int DisassemblerIA32::AVXInstruction(byte* data) {
byte opcode = *data;
byte* current = data + 1;
if (vex_66() && vex_0f38()) {
int mod, regop, rm, vvvv = vex_vreg();
get_modrm(*current, &mod, ®op, &rm);
switch (opcode) {
case 0x18:
AppendToBuffer("vbroadcastss %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x99:
AppendToBuffer("vfmadd132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xA9:
AppendToBuffer("vfmadd213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xB9:
AppendToBuffer("vfmadd231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x9B:
AppendToBuffer("vfmsub132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xAB:
AppendToBuffer("vfmsub213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xBB:
AppendToBuffer("vfmsub231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x9D:
AppendToBuffer("vfnmadd132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xAD:
AppendToBuffer("vfnmadd213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xBD:
AppendToBuffer("vfnmadd231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x9F:
AppendToBuffer("vfnmsub132s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xAF:
AppendToBuffer("vfnmsub213s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xBF:
AppendToBuffer("vfnmsub231s%c %s,%s,", float_size_code(),
NameOfXMMRegister(regop), NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0xF7:
AppendToBuffer("shlx %s,", NameOfCPURegister(regop));
current += PrintRightOperand(current);
AppendToBuffer(",%s", NameOfCPURegister(vvvv));
break;
#define DECLARE_SSE_AVX_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, \
opcode) \
case 0x##opcode: { \
AppendToBuffer("v" #instruction " %s,%s,", NameOfXMMRegister(regop), \
NameOfXMMRegister(vvvv)); \
current += PrintRightXMMOperand(current); \
break; \
}
SSSE3_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
SSE4_INSTRUCTION_LIST(DECLARE_SSE_AVX_DIS_CASE)
#undef DECLARE_SSE_AVX_DIS_CASE
#define DECLARE_SSE_AVX_RM_DIS_CASE(instruction, notUsed1, notUsed2, notUsed3, \
opcode) \
case 0x##opcode: { \
AppendToBuffer("v" #instruction " %s,", NameOfXMMRegister(regop)); \
current += PrintRightXMMOperand(current); \
break; \
}
SSSE3_UNOP_INSTRUCTION_LIST(DECLARE_SSE_AVX_RM_DIS_CASE)
SSE4_RM_INSTRUCTION_LIST(DECLARE_SSE_AVX_RM_DIS_CASE)
#undef DECLARE_SSE_AVX_RM_DIS_CASE
default:
UnimplementedInstruction();
}
} else if (vex_66() && vex_0f3a()) {
int mod, regop, rm, vvvv = vex_vreg();
get_modrm(*current, &mod, ®op, &rm);
switch (opcode) {
case 0x0E:
AppendToBuffer("vpblendw %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
AppendToBuffer(",%d", Imm8_U(current));
current++;
break;
case 0x0F:
AppendToBuffer("vpalignr %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
AppendToBuffer(",%d", Imm8_U(current));
current++;
break;
case 0x14:
AppendToBuffer("vpextrb ");
current += PrintRightOperand(current);
AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(current));
current++;
break;
case 0x15:
AppendToBuffer("vpextrw ");
current += PrintRightOperand(current);
AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(current));
current++;
break;
case 0x16:
AppendToBuffer("vpextrd ");
current += PrintRightOperand(current);
AppendToBuffer(",%s,%d", NameOfXMMRegister(regop), Imm8(current));
current++;
break;
case 0x20:
AppendToBuffer("vpinsrb %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightOperand(current);
AppendToBuffer(",%d", Imm8(current));
current++;
break;
case 0x21:
AppendToBuffer("vinsertps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
AppendToBuffer(",%d", Imm8(current));
current++;
break;
case 0x22:
AppendToBuffer("vpinsrd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightOperand(current);
AppendToBuffer(",%d", Imm8(current));
current++;
break;
default:
UnimplementedInstruction();
}
} else if (vex_f2() && vex_0f()) {
int mod, regop, rm, vvvv = vex_vreg();
get_modrm(*current, &mod, ®op, &rm);
switch (opcode) {
case 0x12:
AppendToBuffer("vmovddup %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x51:
AppendToBuffer("vsqrtsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x58:
AppendToBuffer("vaddsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x59:
AppendToBuffer("vmulsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5C:
AppendToBuffer("vsubsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5D:
AppendToBuffer("vminsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5E:
AppendToBuffer("vdivsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5F:
AppendToBuffer("vmaxsd %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x70:
AppendToBuffer("vpshuflw %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
AppendToBuffer(",%d", Imm8(current));
current++;
break;
case 0x7C:
AppendToBuffer("vhaddps %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
default:
UnimplementedInstruction();
}
} else if (vex_f3() && vex_0f()) {
int mod, regop, rm, vvvv = vex_vreg();
get_modrm(*current, &mod, ®op, &rm);
switch (opcode) {
case 0x51:
AppendToBuffer("vsqrtss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x58:
AppendToBuffer("vaddss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x59:
AppendToBuffer("vmulss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5B:
AppendToBuffer("vcvttps2dq %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
break;
case 0x5C:
AppendToBuffer("vsubss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5D:
AppendToBuffer("vminss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5E:
AppendToBuffer("vdivss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x5F:
AppendToBuffer("vmaxss %s,%s,", NameOfXMMRegister(regop),
NameOfXMMRegister(vvvv));
current += PrintRightXMMOperand(current);
break;
case 0x6f:
AppendToBuffer("vmovdqu %s,", NameOfXMMRegister(regop));
current += PrintRightOperand(current);
break;
case 0x70:
AppendToBuffer("vpshufhw %s,", NameOfXMMRegister(regop));
current += PrintRightXMMOperand(current);
AppendToBuffer(",%d", Imm8(current));
current++;
break;
case 0x7f:
AppendToBuffer("vmovdqu ");
current += PrintRightOperand(current);
AppendToBuffer(",%s", NameOfXMMRegister(regop));
break;
default:
UnimplementedInstruction();
}
} else if (vex_none() && vex_0f38()) {
int mod, regop, rm, vvvv = vex_vreg();
get_modrm(*current, &mod, ®op, &rm);
const char* mnem = "?";
switch (opcode) {
case 0xF2:
AppendToBuffer("andn %s,%s,", NameOfCPURegister(regop),
NameOfCPURegister(vvvv));
current += PrintRightOperand(current);
break;
case 0xF5:
AppendToBuffer("bzhi %s,", NameOfCPURegister(regop));
current += PrintRightOperand(current);
AppendToBuffer(",%s", NameOfCPURegister(vvvv));
break;
case 0xF7:
AppendToBuffer("bextr %s,", NameOfCPURegister(regop));
current += PrintRightOperand(current);
AppendToBuffer(",%s", NameOfCPURegister(vvvv));
break;
case 0xF3:
switch (regop) {
case 1:
mnem = "blsr";
break;
case 2:
mnem = "blsmsk";
break;
case 3:
mnem = "blsi";
break;
default:
UnimplementedInstruction();