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simulator-riscv64.cc
3998 lines (3736 loc) Β· 129 KB
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simulator-riscv64.cc
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// Copyright 2021 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
// Copyright(c) 2010 - 2017,
// The Regents of the University of California(Regents).All Rights Reserved.
//
// Redistribution and use in source and binary forms,
// with or without modification,
// are permitted provided that the following
// conditions are met : 1. Redistributions of source code must retain the
// above copyright notice, this list of conditions and the following
// disclaimer.2. Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following disclaimer in
// the
// documentation and /
// or
// other materials provided with the distribution.3. Neither the name of
// the Regents nor the names of its contributors may be used to endorse
// or
// promote products derived from
// this software without specific prior written permission.
//
// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT,
// INDIRECT, SPECIAL,
// INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
// EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE.THE SOFTWARE AND ACCOMPANYING DOCUMENTATION,
// IF ANY,
// PROVIDED HEREUNDER IS PROVIDED
// "AS IS".REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE,
// SUPPORT, UPDATES, ENHANCEMENTS,
// OR MODIFICATIONS.
// The original source code covered by the above license above has been
// modified significantly by the v8 project authors.
#include "src/execution/riscv64/simulator-riscv64.h"
// Only build the simulator if not compiling for real RISCV hardware.
#if defined(USE_SIMULATOR)
#include <limits.h>
#include <math.h>
#include <stdarg.h>
#include <stdlib.h>
#include "src/base/bits.h"
#include "src/base/vector.h"
#include "src/codegen/assembler-inl.h"
#include "src/codegen/macro-assembler.h"
#include "src/codegen/riscv64/constants-riscv64.h"
#include "src/diagnostics/disasm.h"
#include "src/heap/combined-heap.h"
#include "src/runtime/runtime-utils.h"
#include "src/utils/ostreams.h"
// RVV
// The following code about RVV was based from:
// https://github.com/riscv/riscv-isa-sim
// Copyright (c) 2010-2017, The Regents of the University of California
// (Regents). All Rights Reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// 3. Neither the name of the Regents nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
template <uint64_t N>
struct type_usew_t;
template <>
struct type_usew_t<8> {
using type = uint8_t;
};
template <>
struct type_usew_t<16> {
using type = uint16_t;
};
template <>
struct type_usew_t<32> {
using type = uint32_t;
};
template <>
struct type_usew_t<64> {
using type = uint64_t;
};
template <>
struct type_usew_t<128> {
using type = __uint128_t;
};
template <uint64_t N>
struct type_sew_t;
template <>
struct type_sew_t<8> {
using type = int8_t;
};
template <>
struct type_sew_t<16> {
using type = int16_t;
};
template <>
struct type_sew_t<32> {
using type = int32_t;
};
template <>
struct type_sew_t<64> {
using type = int64_t;
};
template <>
struct type_sew_t<128> {
using type = __int128_t;
};
#define VV_PARAMS(x) \
type_sew_t<x>::type& vd = \
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
#define VV_UPARAMS(x) \
type_usew_t<x>::type& vd = \
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
#define VX_PARAMS(x) \
type_sew_t<x>::type& vd = \
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
#define VX_UPARAMS(x) \
type_usew_t<x>::type& vd = \
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
#define VI_PARAMS(x) \
type_sew_t<x>::type& vd = \
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
#define VI_UPARAMS(x) \
type_usew_t<x>::type& vd = \
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
#define VN_PARAMS(x) \
constexpr int half_x = x >> 1; \
type_sew_t<half_x>::type& vd = \
Rvvelt<type_sew_t<half_x>::type>(rvv_vd_reg(), i, true); \
type_sew_t<x>::type uimm5 = (type_sew_t<x>::type)(instr_.RvvUimm5()); \
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
#define VN_UPARAMS(x) \
constexpr int half_x = x >> 1; \
type_usew_t<half_x>::type& vd = \
Rvvelt<type_usew_t<half_x>::type>(rvv_vd_reg(), i, true); \
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
#define VXI_PARAMS(x) \
type_sew_t<x>::type& vd = \
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
/* Vector Integer Extension */
#define VI_VIE_PARAMS(x, scale) \
if ((x / scale) < 8) UNREACHABLE(); \
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
auto vs2 = Rvvelt<type_sew_t<x / scale>::type>(rvv_vs2_reg(), i);
#define VI_VIE_UPARAMS(x, scale) \
if ((x / scale) < 8) UNREACHABLE(); \
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
auto vs2 = Rvvelt<type_usew_t<x / scale>::type>(rvv_vs2_reg(), i);
namespace v8 {
namespace internal {
DEFINE_LAZY_LEAKY_OBJECT_GETTER(Simulator::GlobalMonitor,
Simulator::GlobalMonitor::Get)
// Util functions.
inline bool HaveSameSign(int64_t a, int64_t b) { return ((a ^ b) >= 0); }
uint32_t get_fcsr_condition_bit(uint32_t cc) {
if (cc == 0) {
return 23;
} else {
return 24 + cc;
}
}
// Generated by Assembler::break_()/stop(), ebreak code is passed as immediate
// field of a subsequent LUI instruction; otherwise returns -1
static inline int32_t get_ebreak_code(Instruction* instr) {
DCHECK(instr->InstructionBits() == kBreakInstr);
byte* cur = reinterpret_cast<byte*>(instr);
Instruction* next_instr = reinterpret_cast<Instruction*>(cur + kInstrSize);
if (next_instr->BaseOpcodeFieldRaw() == RO_LUI)
return (next_instr->Imm20UValue());
else
return -1;
}
// This macro provides a platform independent use of sscanf. The reason for
// SScanF not being implemented in a platform independent was through
// ::v8::internal::OS in the same way as SNPrintF is that the Windows C Run-Time
// Library does not provide vsscanf.
#define SScanF sscanf
// The RiscvDebugger class is used by the simulator while debugging simulated
// code.
class RiscvDebugger {
public:
explicit RiscvDebugger(Simulator* sim) : sim_(sim) {}
void Debug();
// Print all registers with a nice formatting.
void PrintRegs(char name_prefix, int start_index, int end_index);
void PrintAllRegs();
void PrintAllRegsIncludingFPU();
static const Instr kNopInstr = 0x0;
private:
Simulator* sim_;
int64_t GetRegisterValue(int regnum);
int64_t GetFPURegisterValue(int regnum);
float GetFPURegisterValueFloat(int regnum);
double GetFPURegisterValueDouble(int regnum);
bool GetValue(const char* desc, int64_t* value);
};
inline void UNSUPPORTED() {
printf("Sim: Unsupported instruction.\n");
base::OS::Abort();
}
int64_t RiscvDebugger::GetRegisterValue(int regnum) {
if (regnum == kNumSimuRegisters) {
return sim_->get_pc();
} else {
return sim_->get_register(regnum);
}
}
int64_t RiscvDebugger::GetFPURegisterValue(int regnum) {
if (regnum == kNumFPURegisters) {
return sim_->get_pc();
} else {
return sim_->get_fpu_register(regnum);
}
}
float RiscvDebugger::GetFPURegisterValueFloat(int regnum) {
if (regnum == kNumFPURegisters) {
return sim_->get_pc();
} else {
return sim_->get_fpu_register_float(regnum);
}
}
double RiscvDebugger::GetFPURegisterValueDouble(int regnum) {
if (regnum == kNumFPURegisters) {
return sim_->get_pc();
} else {
return sim_->get_fpu_register_double(regnum);
}
}
bool RiscvDebugger::GetValue(const char* desc, int64_t* value) {
int regnum = Registers::Number(desc);
int fpuregnum = FPURegisters::Number(desc);
if (regnum != kInvalidRegister) {
*value = GetRegisterValue(regnum);
return true;
} else if (fpuregnum != kInvalidFPURegister) {
*value = GetFPURegisterValue(fpuregnum);
return true;
} else if (strncmp(desc, "0x", 2) == 0) {
return SScanF(desc + 2, "%" SCNx64, reinterpret_cast<uint64_t*>(value)) ==
1;
} else {
return SScanF(desc, "%" SCNu64, reinterpret_cast<uint64_t*>(value)) == 1;
}
return false;
}
#define REG_INFO(name) \
name, GetRegisterValue(Registers::Number(name)), \
GetRegisterValue(Registers::Number(name))
void RiscvDebugger::PrintRegs(char name_prefix, int start_index,
int end_index) {
base::EmbeddedVector<char, 10> name1, name2;
DCHECK(name_prefix == 'a' || name_prefix == 't' || name_prefix == 's');
DCHECK(start_index >= 0 && end_index <= 99);
int num_registers = (end_index - start_index) + 1;
for (int i = 0; i < num_registers / 2; i++) {
SNPrintF(name1, "%c%d", name_prefix, start_index + 2 * i);
SNPrintF(name2, "%c%d", name_prefix, start_index + 2 * i + 1);
PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 " \t%3s: 0x%016" PRIx64
" %14" PRId64 " \n",
REG_INFO(name1.begin()), REG_INFO(name2.begin()));
}
if (num_registers % 2 == 1) {
SNPrintF(name1, "%c%d", name_prefix, end_index);
PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 " \n", REG_INFO(name1.begin()));
}
}
void RiscvDebugger::PrintAllRegs() {
PrintF("\n");
// ra, sp, gp
PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 "\t%3s: 0x%016" PRIx64 " %14" PRId64
"\t%3s: 0x%016" PRIx64 " %14" PRId64 "\n",
REG_INFO("ra"), REG_INFO("sp"), REG_INFO("gp"));
// tp, fp, pc
PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 "\t%3s: 0x%016" PRIx64 " %14" PRId64
"\t%3s: 0x%016" PRIx64 " %14" PRId64 "\n",
REG_INFO("tp"), REG_INFO("fp"), REG_INFO("pc"));
// print register a0, .., a7
PrintRegs('a', 0, 7);
// print registers s1, ..., s11
PrintRegs('s', 1, 11);
// print registers t0, ..., t6
PrintRegs('t', 0, 6);
}
#undef REG_INFO
void RiscvDebugger::PrintAllRegsIncludingFPU() {
#define FPU_REG_INFO(n) \
FPURegisters::Name(n), GetFPURegisterValue(n), GetFPURegisterValueDouble(n)
PrintAllRegs();
PrintF("\n\n");
// f0, f1, f2, ... f31.
DCHECK_EQ(kNumFPURegisters % 2, 0);
for (int i = 0; i < kNumFPURegisters; i += 2)
PrintF("%3s: 0x%016" PRIx64 " %16.4e \t%3s: 0x%016" PRIx64 " %16.4e\n",
FPU_REG_INFO(i), FPU_REG_INFO(i + 1));
#undef FPU_REG_INFO
}
void RiscvDebugger::Debug() {
intptr_t last_pc = -1;
bool done = false;
#define COMMAND_SIZE 63
#define ARG_SIZE 255
#define STR(a) #a
#define XSTR(a) STR(a)
char cmd[COMMAND_SIZE + 1];
char arg1[ARG_SIZE + 1];
char arg2[ARG_SIZE + 1];
char* argv[3] = {cmd, arg1, arg2};
// Make sure to have a proper terminating character if reaching the limit.
cmd[COMMAND_SIZE] = 0;
arg1[ARG_SIZE] = 0;
arg2[ARG_SIZE] = 0;
while (!done && (sim_->get_pc() != Simulator::end_sim_pc)) {
if (last_pc != sim_->get_pc()) {
disasm::NameConverter converter;
disasm::Disassembler dasm(converter);
// Use a reasonably large buffer.
v8::base::EmbeddedVector<char, 256> buffer;
const char* name = sim_->builtins_.Lookup((Address)sim_->get_pc());
if (name != nullptr) {
PrintF("Call builtin: %s\n", name);
}
dasm.InstructionDecode(buffer, reinterpret_cast<byte*>(sim_->get_pc()));
PrintF(" 0x%016" PRIx64 " %s\n", sim_->get_pc(), buffer.begin());
last_pc = sim_->get_pc();
}
char* line = ReadLine("sim> ");
if (line == nullptr) {
break;
} else {
char* last_input = sim_->last_debugger_input();
if (strcmp(line, "\n") == 0 && last_input != nullptr) {
line = last_input;
} else {
// Ownership is transferred to sim_;
sim_->set_last_debugger_input(line);
}
// Use sscanf to parse the individual parts of the command line. At the
// moment no command expects more than two parameters.
int argc = SScanF(
line,
"%" XSTR(COMMAND_SIZE) "s "
"%" XSTR(ARG_SIZE) "s "
"%" XSTR(ARG_SIZE) "s",
cmd, arg1, arg2);
if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
Instruction* instr = reinterpret_cast<Instruction*>(sim_->get_pc());
if (!(instr->IsTrap()) ||
instr->InstructionBits() == rtCallRedirInstr) {
sim_->InstructionDecode(
reinterpret_cast<Instruction*>(sim_->get_pc()));
} else {
// Allow si to jump over generated breakpoints.
PrintF("/!\\ Jumping over generated breakpoint.\n");
sim_->set_pc(sim_->get_pc() + kInstrSize);
}
} else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
// Execute the one instruction we broke at with breakpoints disabled.
sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
// Leave the debugger shell.
done = true;
} else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
if (argc == 2) {
int64_t value;
double dvalue;
if (strcmp(arg1, "all") == 0) {
PrintAllRegs();
} else if (strcmp(arg1, "allf") == 0) {
PrintAllRegsIncludingFPU();
} else {
int regnum = Registers::Number(arg1);
int fpuregnum = FPURegisters::Number(arg1);
if (regnum != kInvalidRegister) {
value = GetRegisterValue(regnum);
PrintF("%s: 0x%08" PRIx64 " %" PRId64 " \n", arg1, value,
value);
} else if (fpuregnum != kInvalidFPURegister) {
value = GetFPURegisterValue(fpuregnum);
dvalue = GetFPURegisterValueDouble(fpuregnum);
PrintF("%3s: 0x%016" PRIx64 " %16.4e\n",
FPURegisters::Name(fpuregnum), value, dvalue);
} else {
PrintF("%s unrecognized\n", arg1);
}
}
} else {
if (argc == 3) {
if (strcmp(arg2, "single") == 0) {
int64_t value;
float fvalue;
int fpuregnum = FPURegisters::Number(arg1);
if (fpuregnum != kInvalidFPURegister) {
value = GetFPURegisterValue(fpuregnum);
value &= 0xFFFFFFFFUL;
fvalue = GetFPURegisterValueFloat(fpuregnum);
PrintF("%s: 0x%08" PRIx64 " %11.4e\n", arg1, value, fvalue);
} else {
PrintF("%s unrecognized\n", arg1);
}
} else {
PrintF("print <fpu register> single\n");
}
} else {
PrintF("print <register> or print <fpu register> single\n");
}
}
} else if ((strcmp(cmd, "po") == 0) ||
(strcmp(cmd, "printobject") == 0)) {
if (argc == 2) {
int64_t value;
StdoutStream os;
if (GetValue(arg1, &value)) {
Object obj(value);
os << arg1 << ": \n";
#ifdef DEBUG
obj.Print(os);
os << "\n";
#else
os << Brief(obj) << "\n";
#endif
} else {
os << arg1 << " unrecognized\n";
}
} else {
PrintF("printobject <value>\n");
}
} else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) {
int64_t* cur = nullptr;
int64_t* end = nullptr;
int next_arg = 1;
if (strcmp(cmd, "stack") == 0) {
cur = reinterpret_cast<int64_t*>(sim_->get_register(Simulator::sp));
} else { // Command "mem".
if (argc < 2) {
PrintF("Need to specify <address> to mem command\n");
continue;
}
int64_t value;
if (!GetValue(arg1, &value)) {
PrintF("%s unrecognized\n", arg1);
continue;
}
cur = reinterpret_cast<int64_t*>(value);
next_arg++;
}
int64_t words;
if (argc == next_arg) {
words = 10;
} else {
if (!GetValue(argv[next_arg], &words)) {
words = 10;
}
}
end = cur + words;
while (cur < end) {
PrintF(" 0x%012" PRIxPTR " : 0x%016" PRIx64 " %14" PRId64 " ",
reinterpret_cast<intptr_t>(cur), *cur, *cur);
Object obj(*cur);
Heap* current_heap = sim_->isolate_->heap();
if (obj.IsSmi() ||
IsValidHeapObject(current_heap, HeapObject::cast(obj))) {
PrintF(" (");
if (obj.IsSmi()) {
PrintF("smi %d", Smi::ToInt(obj));
} else {
obj.ShortPrint();
}
PrintF(")");
}
PrintF("\n");
cur++;
}
} else if ((strcmp(cmd, "disasm") == 0) || (strcmp(cmd, "dpc") == 0) ||
(strcmp(cmd, "di") == 0)) {
disasm::NameConverter converter;
disasm::Disassembler dasm(converter);
// Use a reasonably large buffer.
v8::base::EmbeddedVector<char, 256> buffer;
byte* cur = nullptr;
byte* end = nullptr;
if (argc == 1) {
cur = reinterpret_cast<byte*>(sim_->get_pc());
end = cur + (10 * kInstrSize);
} else if (argc == 2) {
int regnum = Registers::Number(arg1);
if (regnum != kInvalidRegister || strncmp(arg1, "0x", 2) == 0) {
// The argument is an address or a register name.
int64_t value;
if (GetValue(arg1, &value)) {
cur = reinterpret_cast<byte*>(value);
// Disassemble 10 instructions at <arg1>.
end = cur + (10 * kInstrSize);
}
} else {
// The argument is the number of instructions.
int64_t value;
if (GetValue(arg1, &value)) {
cur = reinterpret_cast<byte*>(sim_->get_pc());
// Disassemble <arg1> instructions.
end = cur + (value * kInstrSize);
}
}
} else {
int64_t value1;
int64_t value2;
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
cur = reinterpret_cast<byte*>(value1);
end = cur + (value2 * kInstrSize);
}
}
while (cur < end) {
dasm.InstructionDecode(buffer, cur);
PrintF(" 0x%08" PRIxPTR " %s\n", reinterpret_cast<intptr_t>(cur),
buffer.begin());
cur += kInstrSize;
}
} else if (strcmp(cmd, "gdb") == 0) {
PrintF("relinquishing control to gdb\n");
v8::base::OS::DebugBreak();
PrintF("regaining control from gdb\n");
} else if (strcmp(cmd, "break") == 0 || strcmp(cmd, "b") == 0 ||
strcmp(cmd, "tbreak") == 0) {
bool is_tbreak = strcmp(cmd, "tbreak") == 0;
if (argc == 2) {
int64_t value;
if (GetValue(arg1, &value)) {
sim_->SetBreakpoint(reinterpret_cast<Instruction*>(value),
is_tbreak);
} else {
PrintF("%s unrecognized\n", arg1);
}
} else {
sim_->ListBreakpoints();
PrintF("Use `break <address>` to set or disable a breakpoint\n");
PrintF(
"Use `tbreak <address>` to set or disable a temporary "
"breakpoint\n");
}
} else if (strcmp(cmd, "flags") == 0) {
PrintF("No flags on RISC-V !\n");
} else if (strcmp(cmd, "stop") == 0) {
int64_t value;
if (argc == 3) {
// Print information about all/the specified breakpoint(s).
if (strcmp(arg1, "info") == 0) {
if (strcmp(arg2, "all") == 0) {
PrintF("Stop information:\n");
for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
i++) {
sim_->PrintStopInfo(i);
}
} else if (GetValue(arg2, &value)) {
sim_->PrintStopInfo(value);
} else {
PrintF("Unrecognized argument.\n");
}
} else if (strcmp(arg1, "enable") == 0) {
// Enable all/the specified breakpoint(s).
if (strcmp(arg2, "all") == 0) {
for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
i++) {
sim_->EnableStop(i);
}
} else if (GetValue(arg2, &value)) {
sim_->EnableStop(value);
} else {
PrintF("Unrecognized argument.\n");
}
} else if (strcmp(arg1, "disable") == 0) {
// Disable all/the specified breakpoint(s).
if (strcmp(arg2, "all") == 0) {
for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
i++) {
sim_->DisableStop(i);
}
} else if (GetValue(arg2, &value)) {
sim_->DisableStop(value);
} else {
PrintF("Unrecognized argument.\n");
}
}
} else {
PrintF("Wrong usage. Use help command for more information.\n");
}
} else if ((strcmp(cmd, "stat") == 0) || (strcmp(cmd, "st") == 0)) {
// Print registers and disassemble.
PrintAllRegs();
PrintF("\n");
disasm::NameConverter converter;
disasm::Disassembler dasm(converter);
// Use a reasonably large buffer.
v8::base::EmbeddedVector<char, 256> buffer;
byte* cur = nullptr;
byte* end = nullptr;
if (argc == 1) {
cur = reinterpret_cast<byte*>(sim_->get_pc());
end = cur + (10 * kInstrSize);
} else if (argc == 2) {
int64_t value;
if (GetValue(arg1, &value)) {
cur = reinterpret_cast<byte*>(value);
// no length parameter passed, assume 10 instructions
end = cur + (10 * kInstrSize);
}
} else {
int64_t value1;
int64_t value2;
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
cur = reinterpret_cast<byte*>(value1);
end = cur + (value2 * kInstrSize);
}
}
while (cur < end) {
dasm.InstructionDecode(buffer, cur);
PrintF(" 0x%08" PRIxPTR " %s\n", reinterpret_cast<intptr_t>(cur),
buffer.begin());
cur += kInstrSize;
}
} else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
PrintF("cont (alias 'c')\n");
PrintF(" Continue execution\n");
PrintF("stepi (alias 'si')\n");
PrintF(" Step one instruction\n");
PrintF("print (alias 'p')\n");
PrintF(" print <register>\n");
PrintF(" Print register content\n");
PrintF(" Use register name 'all' to print all GPRs\n");
PrintF(" Use register name 'allf' to print all GPRs and FPRs\n");
PrintF("printobject (alias 'po')\n");
PrintF(" printobject <register>\n");
PrintF(" Print an object from a register\n");
PrintF("stack\n");
PrintF(" stack [<words>]\n");
PrintF(" Dump stack content, default dump 10 words)\n");
PrintF("mem\n");
PrintF(" mem <address> [<words>]\n");
PrintF(" Dump memory content, default dump 10 words)\n");
PrintF("flags\n");
PrintF(" print flags\n");
PrintF("disasm (alias 'di')\n");
PrintF(" disasm [<instructions>]\n");
PrintF(" disasm [<address/register>] (e.g., disasm pc) \n");
PrintF(" disasm [[<address/register>] <instructions>]\n");
PrintF(" Disassemble code, default is 10 instructions\n");
PrintF(" from pc\n");
PrintF("gdb \n");
PrintF(" Return to gdb if the simulator was started with gdb\n");
PrintF("break (alias 'b')\n");
PrintF(" break : list all breakpoints\n");
PrintF(" break <address> : set / enable / disable a breakpoint.\n");
PrintF("tbreak\n");
PrintF(" tbreak : list all breakpoints\n");
PrintF(
" tbreak <address> : set / enable / disable a temporary "
"breakpoint.\n");
PrintF(" Set a breakpoint enabled only for one stop. \n");
PrintF("stop feature:\n");
PrintF(" Description:\n");
PrintF(" Stops are debug instructions inserted by\n");
PrintF(" the Assembler::stop() function.\n");
PrintF(" When hitting a stop, the Simulator will\n");
PrintF(" stop and give control to the Debugger.\n");
PrintF(" All stop codes are watched:\n");
PrintF(" - They can be enabled / disabled: the Simulator\n");
PrintF(" will / won't stop when hitting them.\n");
PrintF(" - The Simulator keeps track of how many times they \n");
PrintF(" are met. (See the info command.) Going over a\n");
PrintF(" disabled stop still increases its counter. \n");
PrintF(" Commands:\n");
PrintF(" stop info all/<code> : print infos about number <code>\n");
PrintF(" or all stop(s).\n");
PrintF(" stop enable/disable all/<code> : enables / disables\n");
PrintF(" all or number <code> stop(s)\n");
} else {
PrintF("Unknown command: %s\n", cmd);
}
}
}
#undef COMMAND_SIZE
#undef ARG_SIZE
#undef STR
#undef XSTR
}
void Simulator::SetBreakpoint(Instruction* location, bool is_tbreak) {
for (unsigned i = 0; i < breakpoints_.size(); i++) {
if (breakpoints_.at(i).location == location) {
if (breakpoints_.at(i).is_tbreak != is_tbreak) {
PrintF("Change breakpoint at %p to %s breakpoint\n",
reinterpret_cast<void*>(location),
is_tbreak ? "temporary" : "regular");
breakpoints_.at(i).is_tbreak = is_tbreak;
return;
}
PrintF("Existing breakpoint at %p was %s\n",
reinterpret_cast<void*>(location),
breakpoints_.at(i).enabled ? "disabled" : "enabled");
breakpoints_.at(i).enabled = !breakpoints_.at(i).enabled;
return;
}
}
Breakpoint new_breakpoint = {location, true, is_tbreak};
breakpoints_.push_back(new_breakpoint);
PrintF("Set a %sbreakpoint at %p\n", is_tbreak ? "temporary " : "",
reinterpret_cast<void*>(location));
}
void Simulator::ListBreakpoints() {
PrintF("Breakpoints:\n");
for (unsigned i = 0; i < breakpoints_.size(); i++) {
PrintF("%p : %s %s\n",
reinterpret_cast<void*>(breakpoints_.at(i).location),
breakpoints_.at(i).enabled ? "enabled" : "disabled",
breakpoints_.at(i).is_tbreak ? ": temporary" : "");
}
}
void Simulator::CheckBreakpoints() {
bool hit_a_breakpoint = false;
bool is_tbreak = false;
Instruction* pc_ = reinterpret_cast<Instruction*>(get_pc());
for (unsigned i = 0; i < breakpoints_.size(); i++) {
if ((breakpoints_.at(i).location == pc_) && breakpoints_.at(i).enabled) {
hit_a_breakpoint = true;
if (breakpoints_.at(i).is_tbreak) {
// Disable a temporary breakpoint.
is_tbreak = true;
breakpoints_.at(i).enabled = false;
}
break;
}
}
if (hit_a_breakpoint) {
PrintF("Hit %sa breakpoint at %p.\n", is_tbreak ? "and disabled " : "",
reinterpret_cast<void*>(pc_));
RiscvDebugger dbg(this);
dbg.Debug();
}
}
bool Simulator::ICacheMatch(void* one, void* two) {
DCHECK_EQ(reinterpret_cast<intptr_t>(one) & CachePage::kPageMask, 0);
DCHECK_EQ(reinterpret_cast<intptr_t>(two) & CachePage::kPageMask, 0);
return one == two;
}
static uint32_t ICacheHash(void* key) {
return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
}
static bool AllOnOnePage(uintptr_t start, size_t size) {
intptr_t start_page = (start & ~CachePage::kPageMask);
intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
return start_page == end_page;
}
void Simulator::set_last_debugger_input(char* input) {
DeleteArray(last_debugger_input_);
last_debugger_input_ = input;
}
void Simulator::SetRedirectInstruction(Instruction* instruction) {
instruction->SetInstructionBits(rtCallRedirInstr);
}
void Simulator::FlushICache(base::CustomMatcherHashMap* i_cache,
void* start_addr, size_t size) {
int64_t start = reinterpret_cast<int64_t>(start_addr);
int64_t intra_line = (start & CachePage::kLineMask);
start -= intra_line;
size += intra_line;
size = ((size - 1) | CachePage::kLineMask) + 1;
int offset = (start & CachePage::kPageMask);
while (!AllOnOnePage(start, size - 1)) {
int bytes_to_flush = CachePage::kPageSize - offset;
FlushOnePage(i_cache, start, bytes_to_flush);
start += bytes_to_flush;
size -= bytes_to_flush;
DCHECK_EQ((int64_t)0, start & CachePage::kPageMask);
offset = 0;
}
if (size != 0) {
FlushOnePage(i_cache, start, size);
}
}
CachePage* Simulator::GetCachePage(base::CustomMatcherHashMap* i_cache,
void* page) {
base::HashMap::Entry* entry = i_cache->LookupOrInsert(page, ICacheHash(page));
if (entry->value == nullptr) {
CachePage* new_page = new CachePage();
entry->value = new_page;
}
return reinterpret_cast<CachePage*>(entry->value);
}
// Flush from start up to and not including start + size.
void Simulator::FlushOnePage(base::CustomMatcherHashMap* i_cache,
intptr_t start, size_t size) {
DCHECK_LE(size, CachePage::kPageSize);
DCHECK(AllOnOnePage(start, size - 1));
DCHECK_EQ(start & CachePage::kLineMask, 0);
DCHECK_EQ(size & CachePage::kLineMask, 0);
void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
int offset = (start & CachePage::kPageMask);
CachePage* cache_page = GetCachePage(i_cache, page);
char* valid_bytemap = cache_page->ValidityByte(offset);
memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
}
void Simulator::CheckICache(base::CustomMatcherHashMap* i_cache,
Instruction* instr) {
int64_t address = reinterpret_cast<int64_t>(instr);
void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
int offset = (address & CachePage::kPageMask);
CachePage* cache_page = GetCachePage(i_cache, page);
char* cache_valid_byte = cache_page->ValidityByte(offset);
bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
if (cache_hit) {
// Check that the data in memory matches the contents of the I-cache.
CHECK_EQ(0, memcmp(reinterpret_cast<void*>(instr),
cache_page->CachedData(offset), kInstrSize));
} else {
// Cache miss. Load memory into the cache.
memcpy(cached_line, line, CachePage::kLineLength);
*cache_valid_byte = CachePage::LINE_VALID;
}
}
Simulator::Simulator(Isolate* isolate) : isolate_(isolate), builtins_(isolate) {
// Set up simulator support first. Some of this information is needed to
// setup the architecture state.
stack_size_ = FLAG_sim_stack_size * KB;
stack_ = reinterpret_cast<char*>(malloc(stack_size_));
pc_modified_ = false;
icount_ = 0;
break_count_ = 0;
// Reset debug helpers.
breakpoints_.clear();
// TODO(riscv): 'next' command
// break_on_next_ = false;
// Set up architecture state.
// All registers are initialized to zero to start with.
for (int i = 0; i < kNumSimuRegisters; i++) {
registers_[i] = 0;
}
for (int i = 0; i < kNumFPURegisters; i++) {
FPUregisters_[i] = 0;
}
FCSR_ = 0;
// The sp is initialized to point to the bottom (high address) of the
// allocated stack area. To be safe in potential stack underflows we leave
// some buffer below.
registers_[sp] = reinterpret_cast<int64_t>(stack_) + stack_size_ - 64;
// The ra and pc are initialized to a known bad value that will cause an
// access violation if the simulator ever tries to execute it.
registers_[pc] = bad_ra;
registers_[ra] = bad_ra;
last_debugger_input_ = nullptr;
}
Simulator::~Simulator() {
GlobalMonitor::Get()->RemoveLinkedAddress(&global_monitor_thread_);
free(stack_);
}
// Get the active Simulator for the current thread.
Simulator* Simulator::current(Isolate* isolate) {
v8::internal::Isolate::PerIsolateThreadData* isolate_data =
isolate->FindOrAllocatePerThreadDataForThisThread();
DCHECK_NOT_NULL(isolate_data);
Simulator* sim = isolate_data->simulator();
if (sim == nullptr) {
// TODO(146): delete the simulator object when a thread/isolate goes away.