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assembler-arm.cc
5523 lines (4969 loc) · 192 KB
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assembler-arm.cc
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
// OF THE POSSIBILITY OF SUCH DAMAGE.
// The original source code covered by the above license above has been
// modified significantly by Google Inc.
// Copyright 2012 the V8 project authors. All rights reserved.
#include "src/codegen/arm/assembler-arm.h"
#if V8_TARGET_ARCH_ARM
#include "src/base/bits.h"
#include "src/base/cpu.h"
#include "src/base/overflowing-math.h"
#include "src/codegen/arm/assembler-arm-inl.h"
#include "src/codegen/assembler-inl.h"
#include "src/codegen/machine-type.h"
#include "src/codegen/macro-assembler.h"
#include "src/deoptimizer/deoptimizer.h"
#include "src/objects/objects-inl.h"
namespace v8 {
namespace internal {
static const unsigned kArmv6 = 0u;
static const unsigned kArmv7 = kArmv6 | (1u << ARMv7);
static const unsigned kArmv7WithSudiv = kArmv7 | (1u << ARMv7_SUDIV);
static const unsigned kArmv8 = kArmv7WithSudiv | (1u << ARMv8);
static unsigned CpuFeaturesFromCommandLine() {
unsigned result;
const char* arm_arch = v8_flags.arm_arch;
if (strcmp(arm_arch, "armv8") == 0) {
result = kArmv8;
} else if (strcmp(arm_arch, "armv7+sudiv") == 0) {
result = kArmv7WithSudiv;
} else if (strcmp(arm_arch, "armv7") == 0) {
result = kArmv7;
} else if (strcmp(arm_arch, "armv6") == 0) {
result = kArmv6;
} else {
fprintf(stderr, "Error: unrecognised value for --arm-arch ('%s').\n",
arm_arch);
fprintf(stderr,
"Supported values are: armv8\n"
" armv7+sudiv\n"
" armv7\n"
" armv6\n");
FATAL("arm-arch");
}
// If any of the old (deprecated) flags are specified, print a warning, but
// otherwise try to respect them for now.
// TODO(jbramley): When all the old bots have been updated, remove this.
base::Optional<bool> maybe_enable_armv7 = v8_flags.enable_armv7;
base::Optional<bool> maybe_enable_vfp3 = v8_flags.enable_vfp3;
base::Optional<bool> maybe_enable_32dregs = v8_flags.enable_32dregs;
base::Optional<bool> maybe_enable_neon = v8_flags.enable_neon;
base::Optional<bool> maybe_enable_sudiv = v8_flags.enable_sudiv;
base::Optional<bool> maybe_enable_armv8 = v8_flags.enable_armv8;
if (maybe_enable_armv7.has_value() || maybe_enable_vfp3.has_value() ||
maybe_enable_32dregs.has_value() || maybe_enable_neon.has_value() ||
maybe_enable_sudiv.has_value() || maybe_enable_armv8.has_value()) {
// As an approximation of the old behaviour, set the default values from the
// arm_arch setting, then apply the flags over the top.
bool enable_armv7 = (result & (1u << ARMv7)) != 0;
bool enable_vfp3 = (result & (1u << ARMv7)) != 0;
bool enable_32dregs = (result & (1u << ARMv7)) != 0;
bool enable_neon = (result & (1u << ARMv7)) != 0;
bool enable_sudiv = (result & (1u << ARMv7_SUDIV)) != 0;
bool enable_armv8 = (result & (1u << ARMv8)) != 0;
if (maybe_enable_armv7.has_value()) {
fprintf(stderr,
"Warning: --enable_armv7 is deprecated. "
"Use --arm_arch instead.\n");
enable_armv7 = maybe_enable_armv7.value();
}
if (maybe_enable_vfp3.has_value()) {
fprintf(stderr,
"Warning: --enable_vfp3 is deprecated. "
"Use --arm_arch instead.\n");
enable_vfp3 = maybe_enable_vfp3.value();
}
if (maybe_enable_32dregs.has_value()) {
fprintf(stderr,
"Warning: --enable_32dregs is deprecated. "
"Use --arm_arch instead.\n");
enable_32dregs = maybe_enable_32dregs.value();
}
if (maybe_enable_neon.has_value()) {
fprintf(stderr,
"Warning: --enable_neon is deprecated. "
"Use --arm_arch instead.\n");
enable_neon = maybe_enable_neon.value();
}
if (maybe_enable_sudiv.has_value()) {
fprintf(stderr,
"Warning: --enable_sudiv is deprecated. "
"Use --arm_arch instead.\n");
enable_sudiv = maybe_enable_sudiv.value();
}
if (maybe_enable_armv8.has_value()) {
fprintf(stderr,
"Warning: --enable_armv8 is deprecated. "
"Use --arm_arch instead.\n");
enable_armv8 = maybe_enable_armv8.value();
}
// Emulate the old implications.
if (enable_armv8) {
enable_vfp3 = true;
enable_neon = true;
enable_32dregs = true;
enable_sudiv = true;
}
// Select the best available configuration.
if (enable_armv7 && enable_vfp3 && enable_32dregs && enable_neon) {
if (enable_sudiv) {
if (enable_armv8) {
result = kArmv8;
} else {
result = kArmv7WithSudiv;
}
} else {
result = kArmv7;
}
} else {
result = kArmv6;
}
}
return result;
}
// Get the CPU features enabled by the build.
// For cross compilation the preprocessor symbols such as
// CAN_USE_ARMV7_INSTRUCTIONS and CAN_USE_VFP3_INSTRUCTIONS can be used to
// enable ARMv7 and VFPv3 instructions when building the snapshot. However,
// these flags should be consistent with a supported ARM configuration:
// "armv6": ARMv6 + VFPv2
// "armv7": ARMv7 + VFPv3-D32 + NEON
// "armv7+sudiv": ARMv7 + VFPv4-D32 + NEON + SUDIV
// "armv8": ARMv8 (+ all of the above)
static constexpr unsigned CpuFeaturesFromCompiler() {
// TODO(jbramley): Once the build flags are simplified, these tests should
// also be simplified.
// Check *architectural* implications.
#if defined(CAN_USE_ARMV8_INSTRUCTIONS) && !defined(CAN_USE_ARMV7_INSTRUCTIONS)
#error "CAN_USE_ARMV8_INSTRUCTIONS should imply CAN_USE_ARMV7_INSTRUCTIONS"
#endif
#if defined(CAN_USE_ARMV8_INSTRUCTIONS) && !defined(CAN_USE_SUDIV)
#error "CAN_USE_ARMV8_INSTRUCTIONS should imply CAN_USE_SUDIV"
#endif
#if defined(CAN_USE_ARMV7_INSTRUCTIONS) != defined(CAN_USE_VFP3_INSTRUCTIONS)
// V8 requires VFP, and all ARMv7 devices with VFP have VFPv3. Similarly,
// VFPv3 isn't available before ARMv7.
#error "CAN_USE_ARMV7_INSTRUCTIONS should match CAN_USE_VFP3_INSTRUCTIONS"
#endif
#if defined(CAN_USE_NEON) && !defined(CAN_USE_ARMV7_INSTRUCTIONS)
#error "CAN_USE_NEON should imply CAN_USE_ARMV7_INSTRUCTIONS"
#endif
// Find compiler-implied features.
#if defined(CAN_USE_ARMV8_INSTRUCTIONS) && \
defined(CAN_USE_ARMV7_INSTRUCTIONS) && defined(CAN_USE_SUDIV) && \
defined(CAN_USE_NEON) && defined(CAN_USE_VFP3_INSTRUCTIONS)
return kArmv8;
#elif defined(CAN_USE_ARMV7_INSTRUCTIONS) && defined(CAN_USE_SUDIV) && \
defined(CAN_USE_NEON) && defined(CAN_USE_VFP3_INSTRUCTIONS)
return kArmv7WithSudiv;
#elif defined(CAN_USE_ARMV7_INSTRUCTIONS) && defined(CAN_USE_NEON) && \
defined(CAN_USE_VFP3_INSTRUCTIONS)
return kArmv7;
#else
return kArmv6;
#endif
}
bool CpuFeatures::SupportsWasmSimd128() { return IsSupported(NEON); }
void CpuFeatures::ProbeImpl(bool cross_compile) {
dcache_line_size_ = 64;
unsigned command_line = CpuFeaturesFromCommandLine();
// Only use statically determined features for cross compile (snapshot).
if (cross_compile) {
supported_ |= command_line & CpuFeaturesFromCompiler();
return;
}
#ifndef __arm__
// For the simulator build, use whatever the flags specify.
supported_ |= command_line;
#else // __arm__
// Probe for additional features at runtime.
base::CPU cpu;
// Runtime detection is slightly fuzzy, and some inferences are necessary.
unsigned runtime = kArmv6;
// NEON and VFPv3 imply at least ARMv7-A.
if (cpu.has_neon() && cpu.has_vfp3_d32()) {
DCHECK(cpu.has_vfp3());
runtime |= kArmv7;
if (cpu.has_idiva()) {
runtime |= kArmv7WithSudiv;
if (cpu.architecture() >= 8) {
runtime |= kArmv8;
}
}
}
// Use the best of the features found by CPU detection and those inferred from
// the build system. In both cases, restrict available features using the
// command-line. Note that the command-line flags are very permissive (kArmv8)
// by default.
supported_ |= command_line & CpuFeaturesFromCompiler();
supported_ |= command_line & runtime;
// Additional tuning options.
// ARM Cortex-A9 and Cortex-A5 have 32 byte cachelines.
if (cpu.implementer() == base::CPU::kArm &&
(cpu.part() == base::CPU::kArmCortexA5 ||
cpu.part() == base::CPU::kArmCortexA9)) {
dcache_line_size_ = 32;
}
#endif
DCHECK_IMPLIES(IsSupported(ARMv7_SUDIV), IsSupported(ARMv7));
DCHECK_IMPLIES(IsSupported(ARMv8), IsSupported(ARMv7_SUDIV));
// Set a static value on whether Simd is supported.
// This variable is only used for certain archs to query SupportWasmSimd128()
// at runtime in builtins using an extern ref. Other callers should use
// CpuFeatures::SupportWasmSimd128().
CpuFeatures::supports_wasm_simd_128_ = CpuFeatures::SupportsWasmSimd128();
}
void CpuFeatures::PrintTarget() {
const char* arm_arch = nullptr;
const char* arm_target_type = "";
const char* arm_no_probe = "";
const char* arm_fpu = "";
const char* arm_thumb = "";
const char* arm_float_abi = nullptr;
#if !defined __arm__
arm_target_type = " simulator";
#endif
#if defined ARM_TEST_NO_FEATURE_PROBE
arm_no_probe = " noprobe";
#endif
#if defined CAN_USE_ARMV8_INSTRUCTIONS
arm_arch = "arm v8";
#elif defined CAN_USE_ARMV7_INSTRUCTIONS
arm_arch = "arm v7";
#else
arm_arch = "arm v6";
#endif
#if defined CAN_USE_NEON
arm_fpu = " neon";
#elif defined CAN_USE_VFP3_INSTRUCTIONS
#if defined CAN_USE_VFP32DREGS
arm_fpu = " vfp3";
#else
arm_fpu = " vfp3-d16";
#endif
#else
arm_fpu = " vfp2";
#endif
#ifdef __arm__
arm_float_abi = base::OS::ArmUsingHardFloat() ? "hard" : "softfp";
#elif USE_EABI_HARDFLOAT
arm_float_abi = "hard";
#else
arm_float_abi = "softfp";
#endif
#if defined __arm__ && (defined __thumb__) || (defined __thumb2__)
arm_thumb = " thumb";
#endif
printf("target%s%s %s%s%s %s\n", arm_target_type, arm_no_probe, arm_arch,
arm_fpu, arm_thumb, arm_float_abi);
}
void CpuFeatures::PrintFeatures() {
printf("ARMv8=%d ARMv7=%d VFPv3=%d VFP32DREGS=%d NEON=%d SUDIV=%d",
CpuFeatures::IsSupported(ARMv8), CpuFeatures::IsSupported(ARMv7),
CpuFeatures::IsSupported(VFPv3), CpuFeatures::IsSupported(VFP32DREGS),
CpuFeatures::IsSupported(NEON), CpuFeatures::IsSupported(SUDIV));
#ifdef __arm__
bool eabi_hardfloat = base::OS::ArmUsingHardFloat();
#elif USE_EABI_HARDFLOAT
bool eabi_hardfloat = true;
#else
bool eabi_hardfloat = false;
#endif
printf(" USE_EABI_HARDFLOAT=%d\n", eabi_hardfloat);
}
// -----------------------------------------------------------------------------
// Implementation of RelocInfo
// static
const int RelocInfo::kApplyMask =
RelocInfo::ModeMask(RelocInfo::RELATIVE_CODE_TARGET);
bool RelocInfo::IsCodedSpecially() {
// The deserializer needs to know whether a pointer is specially coded. Being
// specially coded on ARM means that it is a movw/movt instruction. We don't
// generate those for relocatable pointers.
return false;
}
bool RelocInfo::IsInConstantPool() {
return Assembler::is_constant_pool_load(pc_);
}
uint32_t RelocInfo::wasm_call_tag() const {
DCHECK(rmode_ == WASM_CALL || rmode_ == WASM_STUB_CALL);
return static_cast<uint32_t>(
Assembler::target_address_at(pc_, constant_pool_));
}
// -----------------------------------------------------------------------------
// Implementation of Operand and MemOperand
// See assembler-arm-inl.h for inlined constructors
Operand::Operand(Handle<HeapObject> handle) {
rm_ = no_reg;
value_.immediate = static_cast<intptr_t>(handle.address());
rmode_ = RelocInfo::FULL_EMBEDDED_OBJECT;
}
Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
DCHECK(is_uint5(shift_imm));
rm_ = rm;
rs_ = no_reg;
shift_op_ = shift_op;
shift_imm_ = shift_imm & 31;
if ((shift_op == ROR) && (shift_imm == 0)) {
// ROR #0 is functionally equivalent to LSL #0 and this allow us to encode
// RRX as ROR #0 (See below).
shift_op = LSL;
} else if (shift_op == RRX) {
// encoded as ROR with shift_imm == 0
DCHECK_EQ(shift_imm, 0);
shift_op_ = ROR;
shift_imm_ = 0;
}
}
Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
DCHECK(shift_op != RRX);
rm_ = rm;
rs_ = no_reg;
shift_op_ = shift_op;
rs_ = rs;
}
Operand Operand::EmbeddedNumber(double value) {
int32_t smi;
if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
Operand result(0, RelocInfo::FULL_EMBEDDED_OBJECT);
result.is_heap_number_request_ = true;
result.value_.heap_number_request = HeapNumberRequest(value);
return result;
}
MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am)
: rn_(rn), rm_(no_reg), offset_(offset), am_(am) {
// Accesses below the stack pointer are not safe, and are prohibited by the
// ABI. We can check obvious violations here.
if (rn == sp) {
if (am == Offset) DCHECK_LE(0, offset);
if (am == NegOffset) DCHECK_GE(0, offset);
}
}
MemOperand::MemOperand(Register rn, Register rm, AddrMode am)
: rn_(rn), rm_(rm), shift_op_(LSL), shift_imm_(0), am_(am) {}
MemOperand::MemOperand(Register rn, Register rm, ShiftOp shift_op,
int shift_imm, AddrMode am)
: rn_(rn),
rm_(rm),
shift_op_(shift_op),
shift_imm_(shift_imm & 31),
am_(am) {
DCHECK(is_uint5(shift_imm));
}
NeonMemOperand::NeonMemOperand(Register rn, AddrMode am, int align)
: rn_(rn), rm_(am == Offset ? pc : sp) {
DCHECK((am == Offset) || (am == PostIndex));
SetAlignment(align);
}
NeonMemOperand::NeonMemOperand(Register rn, Register rm, int align)
: rn_(rn), rm_(rm) {
SetAlignment(align);
}
void NeonMemOperand::SetAlignment(int align) {
switch (align) {
case 0:
align_ = 0;
break;
case 64:
align_ = 1;
break;
case 128:
align_ = 2;
break;
case 256:
align_ = 3;
break;
default:
UNREACHABLE();
}
}
void Assembler::AllocateAndInstallRequestedHeapNumbers(Isolate* isolate) {
DCHECK_IMPLIES(isolate == nullptr, heap_number_requests_.empty());
for (auto& request : heap_number_requests_) {
Handle<HeapObject> object =
isolate->factory()->NewHeapNumber<AllocationType::kOld>(
request.heap_number());
Address pc = reinterpret_cast<Address>(buffer_start_) + request.offset();
Memory<Address>(constant_pool_entry_address(pc, 0 /* unused */)) =
object.address();
}
}
// -----------------------------------------------------------------------------
// Specific instructions, constants, and masks.
// str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
// register r is not encoded.
const Instr kPushRegPattern = al | B26 | 4 | NegPreIndex | sp.code() * B16;
// ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
// register r is not encoded.
const Instr kPopRegPattern = al | B26 | L | 4 | PostIndex | sp.code() * B16;
// ldr rd, [pc, #offset]
const Instr kLdrPCImmedMask = 15 * B24 | 7 * B20 | 15 * B16;
const Instr kLdrPCImmedPattern = 5 * B24 | L | pc.code() * B16;
// Pc-relative call or jump to a signed imm24 offset.
// bl pc + #offset
// b pc + #offset
const Instr kBOrBlPCImmedMask = 0xE * B24;
const Instr kBOrBlPCImmedPattern = 0xA * B24;
// vldr dd, [pc, #offset]
const Instr kVldrDPCMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8;
const Instr kVldrDPCPattern = 13 * B24 | L | pc.code() * B16 | 11 * B8;
// blxcc rm
const Instr kBlxRegMask =
15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4;
const Instr kBlxRegPattern = B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX;
const Instr kBlxIp = al | kBlxRegPattern | ip.code();
const Instr kMovMvnMask = 0x6D * B21 | 0xF * B16;
const Instr kMovMvnPattern = 0xD * B21;
const Instr kMovMvnFlip = B22;
const Instr kMovLeaveCCMask = 0xDFF * B16;
const Instr kMovLeaveCCPattern = 0x1A0 * B16;
const Instr kMovwPattern = 0x30 * B20;
const Instr kMovtPattern = 0x34 * B20;
const Instr kMovwLeaveCCFlip = 0x5 * B21;
const Instr kMovImmedMask = 0x7F * B21;
const Instr kMovImmedPattern = 0x1D * B21;
const Instr kOrrImmedMask = 0x7F * B21;
const Instr kOrrImmedPattern = 0x1C * B21;
const Instr kCmpCmnMask = 0xDD * B20 | 0xF * B12;
const Instr kCmpCmnPattern = 0x15 * B20;
const Instr kCmpCmnFlip = B21;
const Instr kAddSubFlip = 0x6 * B21;
const Instr kAndBicFlip = 0xE * B21;
// A mask for the Rd register for push, pop, ldr, str instructions.
const Instr kLdrRegFpOffsetPattern = al | B26 | L | Offset | fp.code() * B16;
const Instr kStrRegFpOffsetPattern = al | B26 | Offset | fp.code() * B16;
const Instr kLdrRegFpNegOffsetPattern =
al | B26 | L | NegOffset | fp.code() * B16;
const Instr kStrRegFpNegOffsetPattern = al | B26 | NegOffset | fp.code() * B16;
const Instr kLdrStrInstrTypeMask = 0xFFFF0000;
Assembler::Assembler(const AssemblerOptions& options,
std::unique_ptr<AssemblerBuffer> buffer)
: AssemblerBase(options, std::move(buffer)),
pending_32_bit_constants_(),
scratch_register_list_({ip}) {
reloc_info_writer.Reposition(buffer_start_ + buffer_->size(), pc_);
constant_pool_deadline_ = kMaxInt;
const_pool_blocked_nesting_ = 0;
no_const_pool_before_ = 0;
first_const_pool_32_use_ = -1;
last_bound_pos_ = 0;
if (CpuFeatures::IsSupported(VFP32DREGS)) {
// Register objects tend to be abstracted and survive between scopes, so
// it's awkward to use CpuFeatures::VFP32DREGS with CpuFeatureScope. To make
// its use consistent with other features, we always enable it if we can.
EnableCpuFeature(VFP32DREGS);
// Make sure we pick two D registers which alias a Q register. This way, we
// can use a Q as a scratch if NEON is supported.
scratch_vfp_register_list_ = d14.ToVfpRegList() | d15.ToVfpRegList();
} else {
// When VFP32DREGS is not supported, d15 become allocatable. Therefore we
// cannot use it as a scratch.
scratch_vfp_register_list_ = d14.ToVfpRegList();
}
}
Assembler::~Assembler() {
DCHECK_EQ(const_pool_blocked_nesting_, 0);
DCHECK_EQ(first_const_pool_32_use_, -1);
}
void Assembler::GetCode(Isolate* isolate, CodeDesc* desc,
SafepointTableBuilder* safepoint_table_builder,
int handler_table_offset) {
// As a crutch to avoid having to add manual Align calls wherever we use a
// raw workflow to create Code objects (mostly in tests), add another Align
// call here. It does no harm - the end of the Code object is aligned to the
// (larger) kCodeAlignment anyways.
// TODO(jgruber): Consider moving responsibility for proper alignment to
// metadata table builders (safepoint, handler, constant pool, code
// comments).
DataAlign(Code::kMetadataAlignment);
// Emit constant pool if necessary.
CheckConstPool(true, false);
DCHECK(pending_32_bit_constants_.empty());
int code_comments_size = WriteCodeComments();
AllocateAndInstallRequestedHeapNumbers(isolate);
// Set up code descriptor.
// TODO(jgruber): Reconsider how these offsets and sizes are maintained up to
// this point to make CodeDesc initialization less fiddly.
static constexpr int kConstantPoolSize = 0;
const int instruction_size = pc_offset();
const int code_comments_offset = instruction_size - code_comments_size;
const int constant_pool_offset = code_comments_offset - kConstantPoolSize;
const int handler_table_offset2 = (handler_table_offset == kNoHandlerTable)
? constant_pool_offset
: handler_table_offset;
const int safepoint_table_offset =
(safepoint_table_builder == kNoSafepointTable)
? handler_table_offset2
: safepoint_table_builder->safepoint_table_offset();
const int reloc_info_offset =
static_cast<int>(reloc_info_writer.pos() - buffer_->start());
CodeDesc::Initialize(desc, this, safepoint_table_offset,
handler_table_offset2, constant_pool_offset,
code_comments_offset, reloc_info_offset);
}
void Assembler::Align(int m) {
DCHECK(m >= 4 && base::bits::IsPowerOfTwo(m));
DCHECK_EQ(pc_offset() & (kInstrSize - 1), 0);
while ((pc_offset() & (m - 1)) != 0) {
nop();
}
}
void Assembler::CodeTargetAlign() {
// Preferred alignment of jump targets on some ARM chips.
Align(8);
}
Condition Assembler::GetCondition(Instr instr) {
return Instruction::ConditionField(instr);
}
bool Assembler::IsLdrRegisterImmediate(Instr instr) {
return (instr & (B27 | B26 | B25 | B22 | B20)) == (B26 | B20);
}
bool Assembler::IsVldrDRegisterImmediate(Instr instr) {
return (instr & (15 * B24 | 3 * B20 | 15 * B8)) == (13 * B24 | B20 | 11 * B8);
}
int Assembler::GetLdrRegisterImmediateOffset(Instr instr) {
DCHECK(IsLdrRegisterImmediate(instr));
bool positive = (instr & B23) == B23;
int offset = instr & kOff12Mask; // Zero extended offset.
return positive ? offset : -offset;
}
int Assembler::GetVldrDRegisterImmediateOffset(Instr instr) {
DCHECK(IsVldrDRegisterImmediate(instr));
bool positive = (instr & B23) == B23;
int offset = instr & kOff8Mask; // Zero extended offset.
offset <<= 2;
return positive ? offset : -offset;
}
Instr Assembler::SetLdrRegisterImmediateOffset(Instr instr, int offset) {
DCHECK(IsLdrRegisterImmediate(instr));
bool positive = offset >= 0;
if (!positive) offset = -offset;
DCHECK(is_uint12(offset));
// Set bit indicating whether the offset should be added.
instr = (instr & ~B23) | (positive ? B23 : 0);
// Set the actual offset.
return (instr & ~kOff12Mask) | offset;
}
Instr Assembler::SetVldrDRegisterImmediateOffset(Instr instr, int offset) {
DCHECK(IsVldrDRegisterImmediate(instr));
DCHECK((offset & ~3) == offset); // Must be 64-bit aligned.
bool positive = offset >= 0;
if (!positive) offset = -offset;
DCHECK(is_uint10(offset));
// Set bit indicating whether the offset should be added.
instr = (instr & ~B23) | (positive ? B23 : 0);
// Set the actual offset. Its bottom 2 bits are zero.
return (instr & ~kOff8Mask) | (offset >> 2);
}
bool Assembler::IsStrRegisterImmediate(Instr instr) {
return (instr & (B27 | B26 | B25 | B22 | B20)) == B26;
}
Instr Assembler::SetStrRegisterImmediateOffset(Instr instr, int offset) {
DCHECK(IsStrRegisterImmediate(instr));
bool positive = offset >= 0;
if (!positive) offset = -offset;
DCHECK(is_uint12(offset));
// Set bit indicating whether the offset should be added.
instr = (instr & ~B23) | (positive ? B23 : 0);
// Set the actual offset.
return (instr & ~kOff12Mask) | offset;
}
bool Assembler::IsAddRegisterImmediate(Instr instr) {
return (instr & (B27 | B26 | B25 | B24 | B23 | B22 | B21)) == (B25 | B23);
}
Instr Assembler::SetAddRegisterImmediateOffset(Instr instr, int offset) {
DCHECK(IsAddRegisterImmediate(instr));
DCHECK_GE(offset, 0);
DCHECK(is_uint12(offset));
// Set the offset.
return (instr & ~kOff12Mask) | offset;
}
Register Assembler::GetRd(Instr instr) {
return Register::from_code(Instruction::RdValue(instr));
}
Register Assembler::GetRn(Instr instr) {
return Register::from_code(Instruction::RnValue(instr));
}
Register Assembler::GetRm(Instr instr) {
return Register::from_code(Instruction::RmValue(instr));
}
bool Assembler::IsPush(Instr instr) {
return ((instr & ~kRdMask) == kPushRegPattern);
}
bool Assembler::IsPop(Instr instr) {
return ((instr & ~kRdMask) == kPopRegPattern);
}
bool Assembler::IsStrRegFpOffset(Instr instr) {
return ((instr & kLdrStrInstrTypeMask) == kStrRegFpOffsetPattern);
}
bool Assembler::IsLdrRegFpOffset(Instr instr) {
return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpOffsetPattern);
}
bool Assembler::IsStrRegFpNegOffset(Instr instr) {
return ((instr & kLdrStrInstrTypeMask) == kStrRegFpNegOffsetPattern);
}
bool Assembler::IsLdrRegFpNegOffset(Instr instr) {
return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern);
}
bool Assembler::IsLdrPcImmediateOffset(Instr instr) {
// Check the instruction is indeed a
// ldr<cond> <Rd>, [pc +/- offset_12].
return (instr & kLdrPCImmedMask) == kLdrPCImmedPattern;
}
bool Assembler::IsBOrBlPcImmediateOffset(Instr instr) {
return (instr & kBOrBlPCImmedMask) == kBOrBlPCImmedPattern;
}
bool Assembler::IsVldrDPcImmediateOffset(Instr instr) {
// Check the instruction is indeed a
// vldr<cond> <Dd>, [pc +/- offset_10].
return (instr & kVldrDPCMask) == kVldrDPCPattern;
}
bool Assembler::IsBlxReg(Instr instr) {
// Check the instruction is indeed a
// blxcc <Rm>
return (instr & kBlxRegMask) == kBlxRegPattern;
}
bool Assembler::IsBlxIp(Instr instr) {
// Check the instruction is indeed a
// blx ip
return instr == kBlxIp;
}
bool Assembler::IsTstImmediate(Instr instr) {
return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == (I | TST | S);
}
bool Assembler::IsCmpRegister(Instr instr) {
return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) ==
(CMP | S);
}
bool Assembler::IsCmpImmediate(Instr instr) {
return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == (I | CMP | S);
}
Register Assembler::GetCmpImmediateRegister(Instr instr) {
DCHECK(IsCmpImmediate(instr));
return GetRn(instr);
}
int Assembler::GetCmpImmediateRawImmediate(Instr instr) {
DCHECK(IsCmpImmediate(instr));
return instr & kOff12Mask;
}
// Labels refer to positions in the (to be) generated code.
// There are bound, linked, and unused labels.
//
// Bound labels refer to known positions in the already
// generated code. pos() is the position the label refers to.
//
// Linked labels refer to unknown positions in the code
// to be generated; pos() is the position of the last
// instruction using the label.
//
// The linked labels form a link chain by making the branch offset
// in the instruction steam to point to the previous branch
// instruction using the same label.
//
// The link chain is terminated by a branch offset pointing to the
// same position.
int Assembler::target_at(int pos) {
Instr instr = instr_at(pos);
if (is_uint24(instr)) {
// Emitted link to a label, not part of a branch.
return instr;
}
DCHECK_EQ(5 * B25, instr & 7 * B25); // b, bl, or blx imm24
int imm26 = ((instr & kImm24Mask) << 8) >> 6;
if ((Instruction::ConditionField(instr) == kSpecialCondition) &&
((instr & B24) != 0)) {
// blx uses bit 24 to encode bit 2 of imm26
imm26 += 2;
}
return pos + Instruction::kPcLoadDelta + imm26;
}
void Assembler::target_at_put(int pos, int target_pos) {
Instr instr = instr_at(pos);
if (is_uint24(instr)) {
DCHECK(target_pos == pos || target_pos >= 0);
// Emitted link to a label, not part of a branch.
// Load the position of the label relative to the generated code object
// pointer in a register.
// The existing code must be a single 24-bit label chain link, followed by
// nops encoding the destination register. See mov_label_offset.
// Extract the destination register from the first nop instructions.
Register dst =
Register::from_code(Instruction::RmValue(instr_at(pos + kInstrSize)));
// In addition to the 24-bit label chain link, we expect to find one nop for
// ARMv7 and above, or two nops for ARMv6. See mov_label_offset.
DCHECK(IsNop(instr_at(pos + kInstrSize), dst.code()));
if (!CpuFeatures::IsSupported(ARMv7)) {
DCHECK(IsNop(instr_at(pos + 2 * kInstrSize), dst.code()));
}
// Here are the instructions we need to emit:
// For ARMv7: target24 => target16_1:target16_0
// movw dst, #target16_0
// movt dst, #target16_1
// For ARMv6: target24 => target8_2:target8_1:target8_0
// mov dst, #target8_0
// orr dst, dst, #target8_1 << 8
// orr dst, dst, #target8_2 << 16
uint32_t target24 = target_pos + (Code::kHeaderSize - kHeapObjectTag);
CHECK(is_uint24(target24));
if (is_uint8(target24)) {
// If the target fits in a byte then only patch with a mov
// instruction.
PatchingAssembler patcher(
options(), reinterpret_cast<byte*>(buffer_start_ + pos), 1);
patcher.mov(dst, Operand(target24));
} else {
uint16_t target16_0 = target24 & kImm16Mask;
uint16_t target16_1 = target24 >> 16;
if (CpuFeatures::IsSupported(ARMv7)) {
// Patch with movw/movt.
if (target16_1 == 0) {
PatchingAssembler patcher(
options(), reinterpret_cast<byte*>(buffer_start_ + pos), 1);
CpuFeatureScope scope(&patcher, ARMv7);
patcher.movw(dst, target16_0);
} else {
PatchingAssembler patcher(
options(), reinterpret_cast<byte*>(buffer_start_ + pos), 2);
CpuFeatureScope scope(&patcher, ARMv7);
patcher.movw(dst, target16_0);
patcher.movt(dst, target16_1);
}
} else {
// Patch with a sequence of mov/orr/orr instructions.
uint8_t target8_0 = target16_0 & kImm8Mask;
uint8_t target8_1 = target16_0 >> 8;
uint8_t target8_2 = target16_1 & kImm8Mask;
if (target8_2 == 0) {
PatchingAssembler patcher(
options(), reinterpret_cast<byte*>(buffer_start_ + pos), 2);
patcher.mov(dst, Operand(target8_0));
patcher.orr(dst, dst, Operand(target8_1 << 8));
} else {
PatchingAssembler patcher(
options(), reinterpret_cast<byte*>(buffer_start_ + pos), 3);
patcher.mov(dst, Operand(target8_0));
patcher.orr(dst, dst, Operand(target8_1 << 8));
patcher.orr(dst, dst, Operand(target8_2 << 16));
}
}
}
return;
}
int imm26 = target_pos - (pos + Instruction::kPcLoadDelta);
DCHECK_EQ(5 * B25, instr & 7 * B25); // b, bl, or blx imm24
if (Instruction::ConditionField(instr) == kSpecialCondition) {
// blx uses bit 24 to encode bit 2 of imm26
DCHECK_EQ(0, imm26 & 1);
instr = (instr & ~(B24 | kImm24Mask)) | ((imm26 & 2) >> 1) * B24;
} else {
DCHECK_EQ(0, imm26 & 3);
instr &= ~kImm24Mask;
}
int imm24 = imm26 >> 2;
CHECK(is_int24(imm24));
instr_at_put(pos, instr | (imm24 & kImm24Mask));
}
void Assembler::print(const Label* L) {
if (L->is_unused()) {
PrintF("unused label\n");
} else if (L->is_bound()) {
PrintF("bound label to %d\n", L->pos());
} else if (L->is_linked()) {
Label l;
l.link_to(L->pos());
PrintF("unbound label");
while (l.is_linked()) {
PrintF("@ %d ", l.pos());
Instr instr = instr_at(l.pos());
if ((instr & ~kImm24Mask) == 0) {
PrintF("value\n");
} else {
DCHECK_EQ(instr & 7 * B25, 5 * B25); // b, bl, or blx
Condition cond = Instruction::ConditionField(instr);
const char* b;
const char* c;
if (cond == kSpecialCondition) {
b = "blx";
c = "";
} else {
if ((instr & B24) != 0)
b = "bl";
else
b = "b";
switch (cond) {
case eq:
c = "eq";
break;
case ne:
c = "ne";
break;
case hs:
c = "hs";
break;
case lo:
c = "lo";
break;
case mi:
c = "mi";
break;
case pl:
c = "pl";
break;
case vs:
c = "vs";
break;
case vc:
c = "vc";
break;
case hi:
c = "hi";
break;
case ls:
c = "ls";
break;
case ge:
c = "ge";
break;
case lt:
c = "lt";
break;
case gt:
c = "gt";
break;
case le:
c = "le";
break;
case al:
c = "";
break;
default:
c = "";
UNREACHABLE();
}
}
PrintF("%s%s\n", b, c);
}
next(&l);
}
} else {
PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
}
}
void Assembler::bind_to(Label* L, int pos) {
DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position
while (L->is_linked()) {
int fixup_pos = L->pos();
next(L); // call next before overwriting link with target at fixup_pos
target_at_put(fixup_pos, pos);
}
L->bind_to(pos);
// Keep track of the last bound label so we don't eliminate any instructions
// before a bound label.
if (pos > last_bound_pos_) last_bound_pos_ = pos;
}
void Assembler::bind(Label* L) {
DCHECK(!L->is_bound()); // label can only be bound once
bind_to(L, pc_offset());
}