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assembler-riscv.cc
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assembler-riscv.cc
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// The original source code covered by the above license above has been
// modified significantly by Google Inc.
// Copyright 2021 the V8 project authors. All rights reserved.
#include "src/codegen/riscv/assembler-riscv.h"
#include "src/base/cpu.h"
#include "src/codegen/assembler-inl.h"
#include "src/codegen/safepoint-table.h"
#include "src/codegen/string-constants.h"
#include "src/deoptimizer/deoptimizer.h"
#include "src/diagnostics/disasm.h"
#include "src/diagnostics/disassembler.h"
#include "src/objects/heap-number-inl.h"
namespace v8 {
namespace internal {
// Get the CPU features enabled by the build. For cross compilation the
// preprocessor symbols CAN_USE_FPU_INSTRUCTIONS
// can be defined to enable FPU instructions when building the
// snapshot.
static unsigned CpuFeaturesImpliedByCompiler() {
unsigned answer = 0;
#ifdef CAN_USE_FPU_INSTRUCTIONS
answer |= 1u << FPU;
#endif // def CAN_USE_FPU_INSTRUCTIONS
#if (defined CAN_USE_RVV_INSTRUCTIONS)
answer |= 1u << RISCV_SIMD;
#endif // def CAN_USE_RVV_INSTRUCTIONS
return answer;
}
bool CpuFeatures::SupportsWasmSimd128() { return IsSupported(RISCV_SIMD); }
void CpuFeatures::ProbeImpl(bool cross_compile) {
supported_ |= CpuFeaturesImpliedByCompiler();
// Only use statically determined features for cross compile (snapshot).
if (cross_compile) return;
// Probe for additional features at runtime.
base::CPU cpu;
if (cpu.has_fpu()) supported_ |= 1u << FPU;
if (cpu.has_rvv()) supported_ |= 1u << RISCV_SIMD;
// Set a static value on whether SIMD is supported.
// This variable is only used for certain archs to query SupportWasmSimd128()
// at runtime in builtins using an extern ref. Other callers should use
// CpuFeatures::SupportWasmSimd128().
CpuFeatures::supports_wasm_simd_128_ = CpuFeatures::SupportsWasmSimd128();
}
void CpuFeatures::PrintTarget() {}
void CpuFeatures::PrintFeatures() {}
int ToNumber(Register reg) {
DCHECK(reg.is_valid());
const int kNumbers[] = {
0, // zero_reg
1, // ra
2, // sp
3, // gp
4, // tp
5, // t0
6, // t1
7, // t2
8, // s0/fp
9, // s1
10, // a0
11, // a1
12, // a2
13, // a3
14, // a4
15, // a5
16, // a6
17, // a7
18, // s2
19, // s3
20, // s4
21, // s5
22, // s6
23, // s7
24, // s8
25, // s9
26, // s10
27, // s11
28, // t3
29, // t4
30, // t5
31, // t6
};
return kNumbers[reg.code()];
}
Register ToRegister(int num) {
DCHECK(num >= 0 && num < kNumRegisters);
const Register kRegisters[] = {
zero_reg, ra, sp, gp, tp, t0, t1, t2, fp, s1, a0, a1, a2, a3, a4, a5,
a6, a7, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6};
return kRegisters[num];
}
// -----------------------------------------------------------------------------
// Implementation of RelocInfo.
const int RelocInfo::kApplyMask =
RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE) |
RelocInfo::ModeMask(RelocInfo::NEAR_BUILTIN_ENTRY) |
RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE_ENCODED) |
RelocInfo::ModeMask(RelocInfo::RELATIVE_CODE_TARGET) |
RelocInfo::ModeMask(RelocInfo::CODE_TARGET);
bool RelocInfo::IsCodedSpecially() {
// The deserializer needs to know whether a pointer is specially coded. Being
// specially coded on RISC-V means that it is a lui/addi instruction, and that
// is always the case inside code objects.
return true;
}
bool RelocInfo::IsInConstantPool() { return false; }
uint32_t RelocInfo::wasm_call_tag() const {
DCHECK(rmode_ == WASM_CALL || rmode_ == WASM_STUB_CALL);
return static_cast<uint32_t>(
Assembler::target_address_at(pc_, constant_pool_));
}
// -----------------------------------------------------------------------------
// Implementation of Operand and MemOperand.
// See assembler-riscv-inl.h for inlined constructors.
Operand::Operand(Handle<HeapObject> handle)
: rm_(no_reg), rmode_(RelocInfo::FULL_EMBEDDED_OBJECT) {
value_.immediate = static_cast<intptr_t>(handle.address());
}
Operand Operand::EmbeddedNumber(double value) {
int32_t smi;
if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi));
Operand result(0, RelocInfo::FULL_EMBEDDED_OBJECT);
result.is_heap_number_request_ = true;
result.value_.heap_number_request = HeapNumberRequest(value);
return result;
}
MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) {
offset_ = offset;
}
MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier,
OffsetAddend offset_addend)
: Operand(rm) {
offset_ = unit * multiplier + offset_addend;
}
void Assembler::AllocateAndInstallRequestedHeapNumbers(Isolate* isolate) {
DCHECK_IMPLIES(isolate == nullptr, heap_number_requests_.empty());
for (auto& request : heap_number_requests_) {
Handle<HeapObject> object =
isolate->factory()->NewHeapNumber<AllocationType::kOld>(
request.heap_number());
Address pc = reinterpret_cast<Address>(buffer_start_) + request.offset();
set_target_value_at(pc, reinterpret_cast<uintptr_t>(object.location()));
}
}
// -----------------------------------------------------------------------------
// Specific instructions, constants, and masks.
Assembler::Assembler(const AssemblerOptions& options,
std::unique_ptr<AssemblerBuffer> buffer)
: AssemblerBase(options, std::move(buffer)),
VU(this),
scratch_register_list_({t3, t5}),
constpool_(this) {
reloc_info_writer.Reposition(buffer_start_ + buffer_->size(), pc_);
last_trampoline_pool_end_ = 0;
no_trampoline_pool_before_ = 0;
trampoline_pool_blocked_nesting_ = 0;
// We leave space (16 * kTrampolineSlotsSize)
// for BlockTrampolinePoolScope buffer.
next_buffer_check_ = v8_flags.force_long_branches
? kMaxInt
: kMaxBranchOffset - kTrampolineSlotsSize * 16;
internal_trampoline_exception_ = false;
last_bound_pos_ = 0;
trampoline_emitted_ = v8_flags.force_long_branches;
unbound_labels_count_ = 0;
block_buffer_growth_ = false;
}
void Assembler::AbortedCodeGeneration() { constpool_.Clear(); }
Assembler::~Assembler() { CHECK(constpool_.IsEmpty()); }
void Assembler::GetCode(Isolate* isolate, CodeDesc* desc,
SafepointTableBuilder* safepoint_table_builder,
int handler_table_offset) {
// As a crutch to avoid having to add manual Align calls wherever we use a
// raw workflow to create Code objects (mostly in tests), add another Align
// call here. It does no harm - the end of the Code object is aligned to the
// (larger) kCodeAlignment anyways.
// TODO(jgruber): Consider moving responsibility for proper alignment to
// metadata table builders (safepoint, handler, constant pool, code
// comments).
DataAlign(Code::kMetadataAlignment);
ForceConstantPoolEmissionWithoutJump();
int code_comments_size = WriteCodeComments();
DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
AllocateAndInstallRequestedHeapNumbers(isolate);
// Set up code descriptor.
// TODO(jgruber): Reconsider how these offsets and sizes are maintained up to
// this point to make CodeDesc initialization less fiddly.
static constexpr int kConstantPoolSize = 0;
const int instruction_size = pc_offset();
const int code_comments_offset = instruction_size - code_comments_size;
const int constant_pool_offset = code_comments_offset - kConstantPoolSize;
const int handler_table_offset2 = (handler_table_offset == kNoHandlerTable)
? constant_pool_offset
: handler_table_offset;
const int safepoint_table_offset =
(safepoint_table_builder == kNoSafepointTable)
? handler_table_offset2
: safepoint_table_builder->safepoint_table_offset();
const int reloc_info_offset =
static_cast<int>(reloc_info_writer.pos() - buffer_->start());
CodeDesc::Initialize(desc, this, safepoint_table_offset,
handler_table_offset2, constant_pool_offset,
code_comments_offset, reloc_info_offset);
}
void Assembler::Align(int m) {
DCHECK(m >= 4 && base::bits::IsPowerOfTwo(m));
while ((pc_offset() & (m - 1)) != 0) {
NOP();
}
}
void Assembler::CodeTargetAlign() {
// No advantage to aligning branch/call targets to more than
// single instruction, that I am aware of.
Align(4);
}
// Labels refer to positions in the (to be) generated code.
// There are bound, linked, and unused labels.
//
// Bound labels refer to known positions in the already
// generated code. pos() is the position the label refers to.
//
// Linked labels refer to unknown positions in the code
// to be generated; pos() is the position of the last
// instruction using the label.
// The link chain is terminated by a value in the instruction of 0,
// which is an otherwise illegal value (branch 0 is inf loop). When this case
// is detected, return an position of -1, an otherwise illegal position.
const int kEndOfChain = -1;
const int kEndOfJumpChain = 0;
int Assembler::target_at(int pos, bool is_internal) {
if (is_internal) {
uintptr_t* p = reinterpret_cast<uintptr_t*>(buffer_start_ + pos);
uintptr_t address = *p;
if (address == kEndOfJumpChain) {
return kEndOfChain;
} else {
uintptr_t instr_address = reinterpret_cast<uintptr_t>(p);
DCHECK(instr_address - address < INT_MAX);
int delta = static_cast<int>(instr_address - address);
DCHECK(pos > delta);
return pos - delta;
}
}
Instruction* instruction = Instruction::At(buffer_start_ + pos);
DEBUG_PRINTF("target_at: %p (%d)\n\t",
reinterpret_cast<Instr*>(buffer_start_ + pos), pos);
Instr instr = instruction->InstructionBits();
disassembleInstr(instruction->InstructionBits());
switch (instruction->InstructionOpcodeType()) {
case BRANCH: {
int32_t imm13 = BranchOffset(instr);
if (imm13 == kEndOfJumpChain) {
// EndOfChain sentinel is returned directly, not relative to pc or pos.
return kEndOfChain;
} else {
return pos + imm13;
}
}
case JAL: {
int32_t imm21 = JumpOffset(instr);
if (imm21 == kEndOfJumpChain) {
// EndOfChain sentinel is returned directly, not relative to pc or pos.
return kEndOfChain;
} else {
return pos + imm21;
}
}
case JALR: {
int32_t imm12 = instr >> 20;
if (imm12 == kEndOfJumpChain) {
// EndOfChain sentinel is returned directly, not relative to pc or pos.
return kEndOfChain;
} else {
return pos + imm12;
}
}
case LUI: {
Address pc = reinterpret_cast<Address>(buffer_start_ + pos);
pc = target_address_at(pc);
uintptr_t instr_address =
reinterpret_cast<uintptr_t>(buffer_start_ + pos);
uintptr_t imm = reinterpret_cast<uintptr_t>(pc);
if (imm == kEndOfJumpChain) {
return kEndOfChain;
} else {
DCHECK(instr_address - imm < INT_MAX);
int32_t delta = static_cast<int32_t>(instr_address - imm);
DCHECK(pos > delta);
return pos - delta;
}
}
case AUIPC: {
Instr instr_auipc = instr;
Instr instr_I = instr_at(pos + 4);
DCHECK(IsJalr(instr_I) || IsAddi(instr_I));
int32_t offset = BrachlongOffset(instr_auipc, instr_I);
if (offset == kEndOfJumpChain) return kEndOfChain;
return offset + pos;
}
case RO_C_J: {
int32_t offset = instruction->RvcImm11CJValue();
if (offset == kEndOfJumpChain) return kEndOfChain;
return offset + pos;
}
case RO_C_BNEZ:
case RO_C_BEQZ: {
int32_t offset = instruction->RvcImm8BValue();
if (offset == kEndOfJumpChain) return kEndOfChain;
return pos + offset;
}
default: {
if (instr == kEndOfJumpChain) {
return kEndOfChain;
} else {
int32_t imm18 =
((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
return (imm18 + pos);
}
}
}
}
static inline Instr SetBranchOffset(int32_t pos, int32_t target_pos,
Instr instr) {
int32_t imm = target_pos - pos;
DCHECK_EQ(imm & 1, 0);
DCHECK(is_intn(imm, Assembler::kBranchOffsetBits));
instr &= ~kBImm12Mask;
int32_t imm12 = ((imm & 0x800) >> 4) | // bit 11
((imm & 0x1e) << 7) | // bits 4-1
((imm & 0x7e0) << 20) | // bits 10-5
((imm & 0x1000) << 19); // bit 12
return instr | (imm12 & kBImm12Mask);
}
static inline Instr SetLoadOffset(int32_t offset, Instr instr) {
#if V8_TARGET_ARCH_RISCV64
DCHECK(Assembler::IsLd(instr));
#elif V8_TARGET_ARCH_RISCV32
DCHECK(Assembler::IsLw(instr));
#endif
DCHECK(is_int12(offset));
instr &= ~kImm12Mask;
int32_t imm12 = offset << kImm12Shift;
return instr | (imm12 & kImm12Mask);
}
static inline Instr SetAuipcOffset(int32_t offset, Instr instr) {
DCHECK(Assembler::IsAuipc(instr));
DCHECK(is_int20(offset));
instr = (instr & ~kImm31_12Mask) | ((offset & kImm19_0Mask) << 12);
return instr;
}
static inline Instr SetJalrOffset(int32_t offset, Instr instr) {
DCHECK(Assembler::IsJalr(instr));
DCHECK(is_int12(offset));
instr &= ~kImm12Mask;
int32_t imm12 = offset << kImm12Shift;
DCHECK(Assembler::IsJalr(instr | (imm12 & kImm12Mask)));
DCHECK_EQ(Assembler::JalrOffset(instr | (imm12 & kImm12Mask)), offset);
return instr | (imm12 & kImm12Mask);
}
static inline Instr SetJalOffset(int32_t pos, int32_t target_pos, Instr instr) {
DCHECK(Assembler::IsJal(instr));
int32_t imm = target_pos - pos;
DCHECK_EQ(imm & 1, 0);
DCHECK(is_intn(imm, Assembler::kJumpOffsetBits));
instr &= ~kImm20Mask;
int32_t imm20 = (imm & 0xff000) | // bits 19-12
((imm & 0x800) << 9) | // bit 11
((imm & 0x7fe) << 20) | // bits 10-1
((imm & 0x100000) << 11); // bit 20
return instr | (imm20 & kImm20Mask);
}
static inline ShortInstr SetCJalOffset(int32_t pos, int32_t target_pos,
Instr instr) {
DCHECK(Assembler::IsCJal(instr));
int32_t imm = target_pos - pos;
DCHECK_EQ(imm & 1, 0);
DCHECK(is_intn(imm, Assembler::kCJalOffsetBits));
instr &= ~kImm11Mask;
int16_t imm11 = ((imm & 0x800) >> 1) | ((imm & 0x400) >> 4) |
((imm & 0x300) >> 1) | ((imm & 0x80) >> 3) |
((imm & 0x40) >> 1) | ((imm & 0x20) >> 5) |
((imm & 0x10) << 5) | (imm & 0xe);
imm11 = imm11 << kImm11Shift;
DCHECK(Assembler::IsCJal(instr | (imm11 & kImm11Mask)));
return instr | (imm11 & kImm11Mask);
}
static inline Instr SetCBranchOffset(int32_t pos, int32_t target_pos,
Instr instr) {
DCHECK(Assembler::IsCBranch(instr));
int32_t imm = target_pos - pos;
DCHECK_EQ(imm & 1, 0);
DCHECK(is_intn(imm, Assembler::kCBranchOffsetBits));
instr &= ~kRvcBImm8Mask;
int32_t imm8 = ((imm & 0x20) >> 5) | ((imm & 0x6)) | ((imm & 0xc0) >> 3) |
((imm & 0x18) << 2) | ((imm & 0x100) >> 1);
imm8 = ((imm8 & 0x1f) << 2) | ((imm8 & 0xe0) << 5);
DCHECK(Assembler::IsCBranch(instr | imm8 & kRvcBImm8Mask));
return instr | (imm8 & kRvcBImm8Mask);
}
// We have to use a temporary register for things that can be relocated even
// if they can be encoded in RISC-V's 12 bits of immediate-offset instruction
// space. There is no guarantee that the relocated location can be similarly
// encoded.
bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
return !RelocInfo::IsNoInfo(rmode);
}
void Assembler::disassembleInstr(Instr instr) {
if (!v8_flags.riscv_debug) return;
disasm::NameConverter converter;
disasm::Disassembler disasm(converter);
base::EmbeddedVector<char, 128> disasm_buffer;
disasm.InstructionDecode(disasm_buffer, reinterpret_cast<byte*>(&instr));
DEBUG_PRINTF("%s\n", disasm_buffer.begin());
}
void Assembler::target_at_put(int pos, int target_pos, bool is_internal,
bool trampoline) {
if (is_internal) {
uintptr_t imm = reinterpret_cast<uintptr_t>(buffer_start_) + target_pos;
*reinterpret_cast<uintptr_t*>(buffer_start_ + pos) = imm;
return;
}
DEBUG_PRINTF("\ttarget_at_put: %p (%d) to %p (%d)\n",
reinterpret_cast<Instr*>(buffer_start_ + pos), pos,
reinterpret_cast<Instr*>(buffer_start_ + target_pos),
target_pos);
Instruction* instruction = Instruction::At(buffer_start_ + pos);
Instr instr = instruction->InstructionBits();
switch (instruction->InstructionOpcodeType()) {
case BRANCH: {
instr = SetBranchOffset(pos, target_pos, instr);
instr_at_put(pos, instr);
} break;
case JAL: {
DCHECK(IsJal(instr));
instr = SetJalOffset(pos, target_pos, instr);
instr_at_put(pos, instr);
} break;
case LUI: {
Address pc = reinterpret_cast<Address>(buffer_start_ + pos);
set_target_value_at(
pc, reinterpret_cast<uintptr_t>(buffer_start_ + target_pos));
} break;
case AUIPC: {
Instr instr_auipc = instr;
Instr instr_I = instr_at(pos + 4);
DCHECK(IsJalr(instr_I) || IsAddi(instr_I));
intptr_t offset = target_pos - pos;
if (is_int21(offset) && IsJalr(instr_I) && trampoline) {
DCHECK(is_int21(offset) && ((offset & 1) == 0));
Instr instr = JAL;
instr = SetJalOffset(pos, target_pos, instr);
DCHECK(IsJal(instr));
DCHECK(JumpOffset(instr) == offset);
instr_at_put(pos, instr);
instr_at_put(pos + 4, kNopByte);
} else {
CHECK(is_int32(offset + 0x800));
int32_t Hi20 = (((int32_t)offset + 0x800) >> 12);
int32_t Lo12 = (int32_t)offset << 20 >> 20;
instr_auipc =
(instr_auipc & ~kImm31_12Mask) | ((Hi20 & kImm19_0Mask) << 12);
instr_at_put(pos, instr_auipc);
const int kImm31_20Mask = ((1 << 12) - 1) << 20;
const int kImm11_0Mask = ((1 << 12) - 1);
instr_I = (instr_I & ~kImm31_20Mask) | ((Lo12 & kImm11_0Mask) << 20);
instr_at_put(pos + 4, instr_I);
}
} break;
case RO_C_J: {
ShortInstr short_instr = SetCJalOffset(pos, target_pos, instr);
instr_at_put(pos, short_instr);
} break;
case RO_C_BNEZ:
case RO_C_BEQZ: {
instr = SetCBranchOffset(pos, target_pos, instr);
instr_at_put(pos, instr);
} break;
default: {
// Emitted label constant, not part of a branch.
// Make label relative to Code pointer of generated Code object.
instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
} break;
}
disassembleInstr(instr);
}
void Assembler::print(const Label* L) {
if (L->is_unused()) {
PrintF("unused label\n");
} else if (L->is_bound()) {
PrintF("bound label to %d\n", L->pos());
} else if (L->is_linked()) {
Label l;
l.link_to(L->pos());
PrintF("unbound label");
while (l.is_linked()) {
PrintF("@ %d ", l.pos());
Instr instr = instr_at(l.pos());
if ((instr & ~kImm16Mask) == 0) {
PrintF("value\n");
} else {
PrintF("%d\n", instr);
}
next(&l, is_internal_reference(&l));
}
} else {
PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
}
}
void Assembler::bind_to(Label* L, int pos) {
DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position.
DEBUG_PRINTF("\tbinding %d to label %p\n", pos, L);
int trampoline_pos = kInvalidSlotPos;
bool is_internal = false;
if (L->is_linked() && !trampoline_emitted_) {
unbound_labels_count_--;
if (!is_internal_reference(L)) {
next_buffer_check_ += kTrampolineSlotsSize;
}
}
while (L->is_linked()) {
int fixup_pos = L->pos();
int dist = pos - fixup_pos;
is_internal = is_internal_reference(L);
next(L, is_internal); // Call next before overwriting link with target
// at fixup_pos.
Instr instr = instr_at(fixup_pos);
DEBUG_PRINTF("\tfixup: %d to %d\n", fixup_pos, dist);
if (is_internal) {
target_at_put(fixup_pos, pos, is_internal);
} else {
if (IsBranch(instr)) {
if (dist > kMaxBranchOffset) {
if (trampoline_pos == kInvalidSlotPos) {
trampoline_pos = get_trampoline_entry(fixup_pos);
CHECK_NE(trampoline_pos, kInvalidSlotPos);
}
CHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset);
DEBUG_PRINTF("\t\ttrampolining: %d\n", trampoline_pos);
target_at_put(fixup_pos, trampoline_pos, false, true);
fixup_pos = trampoline_pos;
}
target_at_put(fixup_pos, pos, false);
} else if (IsJal(instr)) {
if (dist > kMaxJumpOffset) {
if (trampoline_pos == kInvalidSlotPos) {
trampoline_pos = get_trampoline_entry(fixup_pos);
CHECK_NE(trampoline_pos, kInvalidSlotPos);
}
CHECK((trampoline_pos - fixup_pos) <= kMaxJumpOffset);
DEBUG_PRINTF("\t\ttrampolining: %d\n", trampoline_pos);
target_at_put(fixup_pos, trampoline_pos, false, true);
fixup_pos = trampoline_pos;
}
target_at_put(fixup_pos, pos, false);
} else {
target_at_put(fixup_pos, pos, false);
}
}
}
L->bind_to(pos);
// Keep track of the last bound label so we don't eliminate any instructions
// before a bound label.
if (pos > last_bound_pos_) last_bound_pos_ = pos;
}
void Assembler::bind(Label* L) {
DCHECK(!L->is_bound()); // Label can only be bound once.
bind_to(L, pc_offset());
}
void Assembler::next(Label* L, bool is_internal) {
DCHECK(L->is_linked());
int link = target_at(L->pos(), is_internal);
if (link == kEndOfChain) {
L->Unuse();
} else {
DCHECK_GE(link, 0);
DEBUG_PRINTF("\tnext: %p to %p (%d)\n", L,
reinterpret_cast<Instr*>(buffer_start_ + link), link);
L->link_to(link);
}
}
bool Assembler::is_near(Label* L) {
DCHECK(L->is_bound());
return is_intn((pc_offset() - L->pos()), kJumpOffsetBits);
}
bool Assembler::is_near(Label* L, OffsetSize bits) {
if (L == nullptr || !L->is_bound()) return true;
return is_intn((pc_offset() - L->pos()), bits);
}
bool Assembler::is_near_branch(Label* L) {
DCHECK(L->is_bound());
return is_intn((pc_offset() - L->pos()), kBranchOffsetBits);
}
int Assembler::BranchOffset(Instr instr) {
// | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode |
// 31 25 11 7
int32_t imm13 = ((instr & 0xf00) >> 7) | ((instr & 0x7e000000) >> 20) |
((instr & 0x80) << 4) | ((instr & 0x80000000) >> 19);
imm13 = imm13 << 19 >> 19;
return imm13;
}
int Assembler::BrachlongOffset(Instr auipc, Instr instr_I) {
DCHECK(reinterpret_cast<Instruction*>(&instr_I)->InstructionType() ==
InstructionBase::kIType);
DCHECK(IsAuipc(auipc));
DCHECK_EQ((auipc & kRdFieldMask) >> kRdShift,
(instr_I & kRs1FieldMask) >> kRs1Shift);
int32_t imm_auipc = AuipcOffset(auipc);
int32_t imm12 = static_cast<int32_t>(instr_I & kImm12Mask) >> 20;
int32_t offset = imm12 + imm_auipc;
return offset;
}
int Assembler::PatchBranchlongOffset(Address pc, Instr instr_auipc,
Instr instr_jalr, int32_t offset) {
DCHECK(IsAuipc(instr_auipc));
DCHECK(IsJalr(instr_jalr));
CHECK(is_int32(offset + 0x800));
int32_t Hi20 = (((int32_t)offset + 0x800) >> 12);
int32_t Lo12 = (int32_t)offset << 20 >> 20;
instr_at_put(pc, SetAuipcOffset(Hi20, instr_auipc));
instr_at_put(pc + 4, SetJalrOffset(Lo12, instr_jalr));
DCHECK(offset ==
BrachlongOffset(Assembler::instr_at(pc), Assembler::instr_at(pc + 4)));
return 2;
}
// Returns the next free trampoline entry.
int32_t Assembler::get_trampoline_entry(int32_t pos) {
int32_t trampoline_entry = kInvalidSlotPos;
if (!internal_trampoline_exception_) {
DEBUG_PRINTF("\tstart: %d,pos: %d\n", trampoline_.start(), pos);
if (trampoline_.start() > pos) {
trampoline_entry = trampoline_.take_slot();
}
if (kInvalidSlotPos == trampoline_entry) {
internal_trampoline_exception_ = true;
}
}
return trampoline_entry;
}
uintptr_t Assembler::jump_address(Label* L) {
intptr_t target_pos;
DEBUG_PRINTF("\tjump_address: %p to %p (%d)\n", L,
reinterpret_cast<Instr*>(buffer_start_ + pc_offset()),
pc_offset());
if (L->is_bound()) {
target_pos = L->pos();
} else {
if (L->is_linked()) {
target_pos = L->pos(); // L's link.
L->link_to(pc_offset());
} else {
L->link_to(pc_offset());
if (!trampoline_emitted_) {
unbound_labels_count_++;
next_buffer_check_ -= kTrampolineSlotsSize;
}
DEBUG_PRINTF("\tstarted link\n");
return kEndOfJumpChain;
}
}
uintptr_t imm = reinterpret_cast<uintptr_t>(buffer_start_) + target_pos;
if (v8_flags.riscv_c_extension)
DCHECK_EQ(imm & 1, 0);
else
DCHECK_EQ(imm & 3, 0);
return imm;
}
int32_t Assembler::branch_long_offset(Label* L) {
intptr_t target_pos;
DEBUG_PRINTF("\tbranch_long_offset: %p to %p (%d)\n", L,
reinterpret_cast<Instr*>(buffer_start_ + pc_offset()),
pc_offset());
if (L->is_bound()) {
target_pos = L->pos();
} else {
if (L->is_linked()) {
target_pos = L->pos(); // L's link.
L->link_to(pc_offset());
} else {
L->link_to(pc_offset());
if (!trampoline_emitted_) {
unbound_labels_count_++;
next_buffer_check_ -= kTrampolineSlotsSize;
}
DEBUG_PRINTF("\tstarted link\n");
return kEndOfJumpChain;
}
}
intptr_t offset = target_pos - pc_offset();
if (v8_flags.riscv_c_extension)
DCHECK_EQ(offset & 1, 0);
else
DCHECK_EQ(offset & 3, 0);
DCHECK(is_int32(offset));
VU.clear();
return static_cast<int32_t>(offset);
}
int32_t Assembler::branch_offset_helper(Label* L, OffsetSize bits) {
int32_t target_pos;
DEBUG_PRINTF("\tbranch_offset_helper: %p to %p (%d)\n", L,
reinterpret_cast<Instr*>(buffer_start_ + pc_offset()),
pc_offset());
if (L->is_bound()) {
target_pos = L->pos();
DEBUG_PRINTF("\tbound: %d", target_pos);
} else {
if (L->is_linked()) {
target_pos = L->pos();
L->link_to(pc_offset());
DEBUG_PRINTF("\tadded to link: %d\n", target_pos);
} else {
L->link_to(pc_offset());
if (!trampoline_emitted_) {
unbound_labels_count_++;
next_buffer_check_ -= kTrampolineSlotsSize;
}
DEBUG_PRINTF("\tstarted link\n");
return kEndOfJumpChain;
}
}
int32_t offset = target_pos - pc_offset();
DCHECK(is_intn(offset, bits));
DCHECK_EQ(offset & 1, 0);
DEBUG_PRINTF("\toffset = %d\n", offset);
VU.clear();
return offset;
}
void Assembler::label_at_put(Label* L, int at_offset) {
int target_pos;
DEBUG_PRINTF("\tlabel_at_put: %p @ %p (%d)\n", L,
reinterpret_cast<Instr*>(buffer_start_ + at_offset), at_offset);
if (L->is_bound()) {
target_pos = L->pos();
instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
} else {
if (L->is_linked()) {
target_pos = L->pos(); // L's link.
int32_t imm18 = target_pos - at_offset;
DCHECK_EQ(imm18 & 3, 0);
int32_t imm16 = imm18 >> 2;
DCHECK(is_int16(imm16));
instr_at_put(at_offset, (int32_t)(imm16 & kImm16Mask));
} else {
target_pos = kEndOfJumpChain;
instr_at_put(at_offset, target_pos);
if (!trampoline_emitted_) {
unbound_labels_count_++;
next_buffer_check_ -= kTrampolineSlotsSize;
}
}
L->link_to(at_offset);
}
}
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
// Definitions for using compressed vs non compressed
void Assembler::NOP() {
if (v8_flags.riscv_c_extension)
c_nop();
else
nop();
}
void Assembler::EBREAK() {
if (v8_flags.riscv_c_extension)
c_ebreak();
else
ebreak();
}
// Assembler Pseudo Instructions (Tables 25.2 and 25.3, RISC-V Unprivileged ISA)
void Assembler::nop() { addi(ToRegister(0), ToRegister(0), 0); }
#if V8_TARGET_ARCH_RISCV64
void Assembler::RV_li(Register rd, int64_t imm) {
// 64-bit imm is put in the register rd.
// In most cases the imm is 32 bit and 2 instructions are generated. If a
// temporary register is available, in the worst case, 6 instructions are
// generated for a full 64-bit immediate. If temporay register is not
// available the maximum will be 8 instructions. If imm is more than 32 bits
// and a temp register is available, imm is divided into two 32-bit parts,
// low_32 and up_32. Each part is built in a separate register. low_32 is
// built before up_32. If low_32 is negative (upper 32 bits are 1), 0xffffffff
// is subtracted from up_32 before up_32 is built. This compensates for 32
// bits of 1's in the lower when the two registers are added. If no temp is
// available, the upper 32 bit is built in rd, and the lower 32 bits are
// devided to 3 parts (11, 11, and 10 bits). The parts are shifted and added
// to the upper part built in rd.
if (is_int32(imm + 0x800)) {
// 32-bit case. Maximum of 2 instructions generated
int64_t high_20 = ((imm + 0x800) >> 12);
int64_t low_12 = imm << 52 >> 52;
if (high_20) {
lui(rd, (int32_t)high_20);
if (low_12) {
addi(rd, rd, low_12);
}
} else {
addi(rd, zero_reg, low_12);
}
return;
} else {
// 64-bit case: divide imm into two 32-bit parts, upper and lower
int64_t up_32 = imm >> 32;
int64_t low_32 = imm & 0xffffffffull;
Register temp_reg = rd;
// Check if a temporary register is available
if (up_32 == 0 || low_32 == 0) {
// No temp register is needed
} else {
UseScratchRegisterScope temps(this);
BlockTrampolinePoolScope block_trampoline_pool(this);
temp_reg = temps.hasAvailable() ? temps.Acquire() : no_reg;
}
if (temp_reg != no_reg) {
// keep track of hardware behavior for lower part in sim_low
int64_t sim_low = 0;
// Build lower part
if (low_32 != 0) {
int64_t high_20 = ((low_32 + 0x800) >> 12);
int64_t low_12 = low_32 & 0xfff;
if (high_20) {
// Adjust to 20 bits for the case of overflow
high_20 &= 0xfffff;
sim_low = ((high_20 << 12) << 32) >> 32;
lui(rd, (int32_t)high_20);
if (low_12) {
sim_low += (low_12 << 52 >> 52) | low_12;
addi(rd, rd, low_12);
}
} else {
sim_low = low_12;
ori(rd, zero_reg, low_12);
}
}
if (sim_low & 0x100000000) {
// Bit 31 is 1. Either an overflow or a negative 64 bit
if (up_32 == 0) {
// Positive number, but overflow because of the add 0x800
slli(rd, rd, 32);
srli(rd, rd, 32);
return;
}
// low_32 is a negative 64 bit after the build
up_32 = (up_32 - 0xffffffff) & 0xffffffff;
}
if (up_32 == 0) {
return;
}
// Build upper part in a temporary register
if (low_32 == 0) {
// Build upper part in rd
temp_reg = rd;
}
int64_t high_20 = (up_32 + 0x800) >> 12;
int64_t low_12 = up_32 & 0xfff;
if (high_20) {
// Adjust to 20 bits for the case of overflow
high_20 &= 0xfffff;
lui(temp_reg, (int32_t)high_20);
if (low_12) {
addi(temp_reg, temp_reg, low_12);
}
} else {
ori(temp_reg, zero_reg, low_12);
}
// Put it at the bgining of register
slli(temp_reg, temp_reg, 32);
if (low_32 != 0) {
add(rd, rd, temp_reg);
}
return;
}
// No temp register. Build imm in rd.
// Build upper 32 bits first in rd. Divide lower 32 bits parts and add
// parts to the upper part by doing shift and add.
// First build upper part in rd.
int64_t high_20 = (up_32 + 0x800) >> 12;
int64_t low_12 = up_32 & 0xfff;
if (high_20) {
// Adjust to 20 bits for the case of overflow
high_20 &= 0xfffff;
lui(rd, (int32_t)high_20);
if (low_12) {
addi(rd, rd, low_12);
}
} else {