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macro-assembler-riscv.cc
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macro-assembler-riscv.cc
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// Copyright 2021 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include <limits.h> // For LONG_MIN, LONG_MAX.
#include "src/base/bits.h"
#include "src/base/division-by-constant.h"
#include "src/codegen/assembler-inl.h"
#include "src/codegen/callable.h"
#include "src/codegen/code-factory.h"
#include "src/codegen/external-reference-table.h"
#include "src/codegen/interface-descriptors-inl.h"
#include "src/codegen/macro-assembler.h"
#include "src/codegen/register-configuration.h"
#include "src/debug/debug.h"
#include "src/deoptimizer/deoptimizer.h"
#include "src/execution/frames-inl.h"
#include "src/heap/memory-chunk.h"
#include "src/init/bootstrapper.h"
#include "src/logging/counters.h"
#include "src/objects/heap-number.h"
#include "src/runtime/runtime.h"
#include "src/snapshot/snapshot.h"
#include "src/wasm/wasm-code-manager.h"
// Satisfy cpplint check, but don't include platform-specific header. It is
// included recursively via macro-assembler.h.
#if 0
#include "src/codegen/riscv/macro-assembler-riscv.h"
#endif
namespace v8 {
namespace internal {
static inline bool IsZero(const Operand& rt) {
if (rt.is_reg()) {
return rt.rm() == zero_reg;
} else {
return rt.immediate() == 0;
}
}
int TurboAssembler::RequiredStackSizeForCallerSaved(SaveFPRegsMode fp_mode,
Register exclusion1,
Register exclusion2,
Register exclusion3) const {
int bytes = 0;
RegList exclusions = {exclusion1, exclusion2, exclusion3};
RegList list = kJSCallerSaved - exclusions;
bytes += list.Count() * kSystemPointerSize;
if (fp_mode == SaveFPRegsMode::kSave) {
bytes += kCallerSavedFPU.Count() * kDoubleSize;
}
return bytes;
}
int TurboAssembler::PushCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1,
Register exclusion2, Register exclusion3) {
int bytes = 0;
RegList exclusions = {exclusion1, exclusion2, exclusion3};
RegList list = kJSCallerSaved - exclusions;
MultiPush(list);
bytes += list.Count() * kSystemPointerSize;
if (fp_mode == SaveFPRegsMode::kSave) {
MultiPushFPU(kCallerSavedFPU);
bytes += kCallerSavedFPU.Count() * kDoubleSize;
}
return bytes;
}
int TurboAssembler::PopCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1,
Register exclusion2, Register exclusion3) {
int bytes = 0;
if (fp_mode == SaveFPRegsMode::kSave) {
MultiPopFPU(kCallerSavedFPU);
bytes += kCallerSavedFPU.Count() * kDoubleSize;
}
RegList exclusions = {exclusion1, exclusion2, exclusion3};
RegList list = kJSCallerSaved - exclusions;
MultiPop(list);
bytes += list.Count() * kSystemPointerSize;
return bytes;
}
#define __ ACCESS_MASM(masm)
namespace {
static void TailCallOptimizedCodeSlot(MacroAssembler* masm,
Register optimized_code_entry,
Register scratch1, Register scratch2) {
// ----------- S t a t e -------------
// -- a0 : actual argument count
// -- a3 : new target (preserved for callee if needed, and caller)
// -- a1 : target function (preserved for callee if needed, and caller)
// -----------------------------------
ASM_CODE_COMMENT(masm);
DCHECK(!AreAliased(optimized_code_entry, a1, a3, scratch1, scratch2));
Register closure = a1;
Label heal_optimized_code_slot;
// If the optimized code is cleared, go to runtime to update the optimization
// marker field.
__ LoadWeakValue(optimized_code_entry, optimized_code_entry,
&heal_optimized_code_slot);
// Check if the optimized code is marked for deopt. If it is, call the
// runtime to clear it.
__ JumpIfCodeTIsMarkedForDeoptimization(optimized_code_entry, scratch1,
&heal_optimized_code_slot);
// Optimized code is good, get it into the closure and link the closure into
// the optimized functions list, then tail call the optimized code.
// The feedback vector is no longer used, so re-use it as a scratch
// register.
__ ReplaceClosureCodeWithOptimizedCode(optimized_code_entry, closure);
static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch");
__ LoadCodeObjectEntry(a2, optimized_code_entry);
__ Jump(a2);
// Optimized code slot contains deoptimized code or code is cleared and
// optimized code marker isn't updated. Evict the code, update the marker
// and re-enter the closure's code.
__ bind(&heal_optimized_code_slot);
__ GenerateTailCallToReturnedCode(Runtime::kHealOptimizedCodeSlot);
}
} // namespace
#ifdef V8_ENABLE_DEBUG_CODE
void MacroAssembler::AssertFeedbackVector(Register object, Register scratch) {
if (v8_flags.debug_code) {
GetObjectType(object, scratch, scratch);
Assert(eq, AbortReason::kExpectedFeedbackVector, scratch,
Operand(FEEDBACK_VECTOR_TYPE));
}
}
#endif // V8_ENABLE_DEBUG_CODE
void MacroAssembler::ReplaceClosureCodeWithOptimizedCode(
Register optimized_code, Register closure) {
ASM_CODE_COMMENT(this);
DCHECK(!AreAliased(optimized_code, closure));
// Store code entry in the closure.
StoreTaggedField(optimized_code,
FieldMemOperand(closure, JSFunction::kCodeOffset));
RecordWriteField(closure, JSFunction::kCodeOffset, optimized_code,
kRAHasNotBeenSaved, SaveFPRegsMode::kIgnore,
SmiCheck::kOmit);
}
void MacroAssembler::GenerateTailCallToReturnedCode(
Runtime::FunctionId function_id) {
// ----------- S t a t e -------------
// -- a0 : actual argument count
// -- a1 : target function (preserved for callee)
// -- a3 : new target (preserved for callee)
// -----------------------------------
{
FrameScope scope(this, StackFrame::INTERNAL);
// Push a copy of the target function, the new target and the actual
// argument count.
// Push function as parameter to the runtime call.
SmiTag(kJavaScriptCallArgCountRegister);
Push(kJavaScriptCallTargetRegister, kJavaScriptCallNewTargetRegister,
kJavaScriptCallArgCountRegister, kJavaScriptCallTargetRegister);
CallRuntime(function_id, 1);
// Use the return value before restoring a0
AddWord(a2, a0, Operand(Code::kHeaderSize - kHeapObjectTag));
// Restore target function, new target and actual argument count.
Pop(kJavaScriptCallTargetRegister, kJavaScriptCallNewTargetRegister,
kJavaScriptCallArgCountRegister);
SmiUntag(kJavaScriptCallArgCountRegister);
}
static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch");
Jump(a2);
}
// Read off the flags in the feedback vector and check if there
// is optimized code or a tiering state that needs to be processed.
void MacroAssembler::LoadFeedbackVectorFlagsAndJumpIfNeedsProcessing(
Register flags, Register feedback_vector, CodeKind current_code_kind,
Label* flags_need_processing) {
ASM_CODE_COMMENT(this);
DCHECK(!AreAliased(flags, feedback_vector));
DCHECK(CodeKindCanTierUp(current_code_kind));
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Lhu(flags, FieldMemOperand(feedback_vector, FeedbackVector::kFlagsOffset));
uint32_t kFlagsMask = FeedbackVector::kFlagsTieringStateIsAnyRequested |
FeedbackVector::kFlagsMaybeHasTurbofanCode |
FeedbackVector::kFlagsLogNextExecution;
if (current_code_kind != CodeKind::MAGLEV) {
kFlagsMask |= FeedbackVector::kFlagsMaybeHasMaglevCode;
}
And(scratch, flags, Operand(kFlagsMask));
Branch(flags_need_processing, ne, scratch, Operand(zero_reg));
}
void MacroAssembler::OptimizeCodeOrTailCallOptimizedCodeSlot(
Register flags, Register feedback_vector) {
ASM_CODE_COMMENT(this);
DCHECK(!AreAliased(flags, feedback_vector));
UseScratchRegisterScope temps(this);
temps.Include(t0, t1);
Label maybe_has_optimized_code, maybe_needs_logging;
// Check if optimized code is available.
{
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
And(scratch, flags,
Operand(FeedbackVector::kFlagsTieringStateIsAnyRequested));
Branch(&maybe_needs_logging, eq, scratch, Operand(zero_reg),
Label::Distance::kNear);
}
GenerateTailCallToReturnedCode(Runtime::kCompileOptimized);
bind(&maybe_needs_logging);
{
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
And(scratch, flags, Operand(FeedbackVector::LogNextExecutionBit::kMask));
Branch(&maybe_has_optimized_code, eq, scratch, Operand(zero_reg),
Label::Distance::kNear);
}
GenerateTailCallToReturnedCode(Runtime::kFunctionLogNextExecution);
bind(&maybe_has_optimized_code);
Register optimized_code_entry = flags;
LoadAnyTaggedField(
optimized_code_entry,
FieldMemOperand(feedback_vector,
FeedbackVector::kMaybeOptimizedCodeOffset));
TailCallOptimizedCodeSlot(this, optimized_code_entry, temps.Acquire(),
temps.Acquire());
}
void TurboAssembler::LoadRoot(Register destination, RootIndex index) {
LoadWord(destination,
MemOperand(kRootRegister, RootRegisterOffsetForRootIndex(index)));
}
void TurboAssembler::LoadRoot(Register destination, RootIndex index,
Condition cond, Register src1,
const Operand& src2) {
Label skip;
BranchShort(&skip, NegateCondition(cond), src1, src2);
LoadWord(destination,
MemOperand(kRootRegister, RootRegisterOffsetForRootIndex(index)));
bind(&skip);
}
void TurboAssembler::PushCommonFrame(Register marker_reg) {
if (marker_reg.is_valid()) {
Push(ra, fp, marker_reg);
AddWord(fp, sp, Operand(kSystemPointerSize));
} else {
Push(ra, fp);
Mv(fp, sp);
}
}
void TurboAssembler::PushStandardFrame(Register function_reg) {
int offset = -StandardFrameConstants::kContextOffset;
if (function_reg.is_valid()) {
Push(ra, fp, cp, function_reg, kJavaScriptCallArgCountRegister);
offset += 2 * kSystemPointerSize;
} else {
Push(ra, fp, cp, kJavaScriptCallArgCountRegister);
offset += kSystemPointerSize;
}
AddWord(fp, sp, Operand(offset));
}
int MacroAssembler::SafepointRegisterStackIndex(int reg_code) {
// The registers are pushed starting with the highest encoding,
// which means that lowest encodings are closest to the stack pointer.
return kSafepointRegisterStackIndexMap[reg_code];
}
// Clobbers object, dst, value, and ra, if (ra_status == kRAHasBeenSaved)
// The register 'object' contains a heap object pointer. The heap object
// tag is shifted away.
void MacroAssembler::RecordWriteField(Register object, int offset,
Register value, RAStatus ra_status,
SaveFPRegsMode save_fp,
SmiCheck smi_check) {
DCHECK(!AreAliased(object, value));
// First, check if a write barrier is even needed. The tests below
// catch stores of Smis.
Label done;
// Skip the barrier if writing a smi.
if (smi_check == SmiCheck::kInline) {
JumpIfSmi(value, &done);
}
// Although the object register is tagged, the offset is relative to the start
// of the object, so offset must be a multiple of kTaggedSize.
DCHECK(IsAligned(offset, kTaggedSize));
if (v8_flags.debug_code) {
Label ok;
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
DCHECK(!AreAliased(object, value, scratch));
AddWord(scratch, object, offset - kHeapObjectTag);
And(scratch, scratch, Operand(kTaggedSize - 1));
BranchShort(&ok, eq, scratch, Operand(zero_reg));
Abort(AbortReason::kUnalignedCellInWriteBarrier);
bind(&ok);
}
RecordWrite(object, Operand(offset - kHeapObjectTag), value, ra_status,
save_fp, SmiCheck::kOmit);
bind(&done);
}
void TurboAssembler::MaybeSaveRegisters(RegList registers) {
if (registers.is_empty()) return;
MultiPush(registers);
}
void TurboAssembler::MaybeRestoreRegisters(RegList registers) {
if (registers.is_empty()) return;
MultiPop(registers);
}
void TurboAssembler::CallEphemeronKeyBarrier(Register object,
Register slot_address,
SaveFPRegsMode fp_mode) {
DCHECK(!AreAliased(object, slot_address));
RegList registers =
WriteBarrierDescriptor::ComputeSavedRegisters(object, slot_address);
MaybeSaveRegisters(registers);
Register object_parameter = WriteBarrierDescriptor::ObjectRegister();
Register slot_address_parameter =
WriteBarrierDescriptor::SlotAddressRegister();
Push(object);
Push(slot_address);
Pop(slot_address_parameter);
Pop(object_parameter);
Call(isolate()->builtins()->code_handle(
Builtins::GetEphemeronKeyBarrierStub(fp_mode)),
RelocInfo::CODE_TARGET);
MaybeRestoreRegisters(registers);
}
void TurboAssembler::CallRecordWriteStubSaveRegisters(Register object,
Register slot_address,
SaveFPRegsMode fp_mode,
StubCallMode mode) {
DCHECK(!AreAliased(object, slot_address));
RegList registers =
WriteBarrierDescriptor::ComputeSavedRegisters(object, slot_address);
MaybeSaveRegisters(registers);
Register object_parameter = WriteBarrierDescriptor::ObjectRegister();
Register slot_address_parameter =
WriteBarrierDescriptor::SlotAddressRegister();
Push(object);
Push(slot_address);
Pop(slot_address_parameter);
Pop(object_parameter);
CallRecordWriteStub(object_parameter, slot_address_parameter, fp_mode, mode);
MaybeRestoreRegisters(registers);
}
void TurboAssembler::CallRecordWriteStub(Register object, Register slot_address,
SaveFPRegsMode fp_mode,
StubCallMode mode) {
// Use CallRecordWriteStubSaveRegisters if the object and slot registers
// need to be caller saved.
DCHECK_EQ(WriteBarrierDescriptor::ObjectRegister(), object);
DCHECK_EQ(WriteBarrierDescriptor::SlotAddressRegister(), slot_address);
if (mode == StubCallMode::kCallWasmRuntimeStub) {
auto wasm_target = wasm::WasmCode::GetRecordWriteStub(fp_mode);
Call(wasm_target, RelocInfo::WASM_STUB_CALL);
} else {
auto builtin = Builtins::GetRecordWriteStub(fp_mode);
CallBuiltin(builtin);
}
}
// Clobbers object, address, value, and ra, if (ra_status == kRAHasBeenSaved)
// The register 'object' contains a heap object pointer. The heap object
// tag is shifted away.
void MacroAssembler::RecordWrite(Register object, Operand offset,
Register value, RAStatus ra_status,
SaveFPRegsMode fp_mode, SmiCheck smi_check) {
DCHECK(!AreAliased(object, value));
if (v8_flags.debug_code) {
UseScratchRegisterScope temps(this);
Register temp = temps.Acquire();
DCHECK(!AreAliased(object, value, temp));
AddWord(temp, object, offset);
LoadTaggedPointerField(temp, MemOperand(temp));
Assert(eq, AbortReason::kWrongAddressOrValuePassedToRecordWrite, temp,
Operand(value));
}
if (v8_flags.disable_write_barriers) {
return;
}
// First, check if a write barrier is even needed. The tests below
// catch stores of smis and stores into the young generation.
Label done;
if (smi_check == SmiCheck::kInline) {
DCHECK_EQ(0, kSmiTag);
JumpIfSmi(value, &done);
}
{
UseScratchRegisterScope temps(this);
Register temp = temps.Acquire();
CheckPageFlag(value,
temp, // Used as scratch.
MemoryChunk::kPointersToHereAreInterestingOrInSharedHeapMask,
eq, // In RISC-V, it uses cc for a comparison with 0, so if
// no bits are set, and cc is eq, it will branch to done
&done);
CheckPageFlag(object,
temp, // Used as scratch.
MemoryChunk::kPointersFromHereAreInterestingMask,
eq, // In RISC-V, it uses cc for a comparison with 0, so if
// no bits are set, and cc is eq, it will branch to done
&done);
}
// Record the actual write.
if (ra_status == kRAHasNotBeenSaved) {
push(ra);
}
Register slot_address = WriteBarrierDescriptor::SlotAddressRegister();
DCHECK(!AreAliased(object, slot_address, value));
// TODO(cbruni): Turn offset into int.
DCHECK(offset.IsImmediate());
AddWord(slot_address, object, offset);
CallRecordWriteStub(object, slot_address, fp_mode);
if (ra_status == kRAHasNotBeenSaved) {
pop(ra);
}
if (v8_flags.debug_code) li(slot_address, Operand(kZapValue));
bind(&done);
}
// ---------------------------------------------------------------------------
// Instruction macros.
#if V8_TARGET_ARCH_RISCV64
void TurboAssembler::Add32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
((rd.code() & 0b11000) == 0b01000) &&
((rt.rm().code() & 0b11000) == 0b01000)) {
c_addw(rd, rt.rm());
} else {
addw(rd, rs, rt.rm());
}
} else {
if (v8_flags.riscv_c_extension && is_int6(rt.immediate()) &&
(rd.code() == rs.code()) && (rd != zero_reg) &&
!MustUseReg(rt.rmode())) {
c_addiw(rd, static_cast<int8_t>(rt.immediate()));
} else if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) {
addiw(rd, rs, static_cast<int32_t>(rt.immediate()));
} else if ((-4096 <= rt.immediate() && rt.immediate() <= -2049) ||
(2048 <= rt.immediate() && rt.immediate() <= 4094)) {
addiw(rd, rs, rt.immediate() / 2);
addiw(rd, rd, rt.immediate() - (rt.immediate() / 2));
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
addw(rd, rs, scratch);
}
}
}
void TurboAssembler::Sub32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
((rd.code() & 0b11000) == 0b01000) &&
((rt.rm().code() & 0b11000) == 0b01000)) {
c_subw(rd, rt.rm());
} else {
subw(rd, rs, rt.rm());
}
} else {
DCHECK(is_int32(rt.immediate()));
if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
(rd != zero_reg) && is_int6(-rt.immediate()) &&
!MustUseReg(rt.rmode())) {
c_addiw(
rd,
static_cast<int8_t>(
-rt.immediate())); // No c_subiw instr, use c_addiw(x, y, -imm).
} else if (is_int12(-rt.immediate()) && !MustUseReg(rt.rmode())) {
addiw(rd, rs,
static_cast<int32_t>(
-rt.immediate())); // No subiw instr, use addiw(x, y, -imm).
} else if ((-4096 <= -rt.immediate() && -rt.immediate() <= -2049) ||
(2048 <= -rt.immediate() && -rt.immediate() <= 4094)) {
addiw(rd, rs, -rt.immediate() / 2);
addiw(rd, rd, -rt.immediate() - (-rt.immediate() / 2));
} else {
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
if (-rt.immediate() >> 12 == 0 && !MustUseReg(rt.rmode())) {
// Use load -imm and addu when loading -imm generates one instruction.
Li(scratch, -rt.immediate());
addw(rd, rs, scratch);
} else {
// li handles the relocation.
Li(scratch, rt.immediate());
subw(rd, rs, scratch);
}
}
}
}
void TurboAssembler::AddWord(Register rd, Register rs, const Operand& rt) {
Add64(rd, rs, rt);
}
void TurboAssembler::SubWord(Register rd, Register rs, const Operand& rt) {
Sub64(rd, rs, rt);
}
void TurboAssembler::Sub64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
((rd.code() & 0b11000) == 0b01000) &&
((rt.rm().code() & 0b11000) == 0b01000)) {
c_sub(rd, rt.rm());
} else {
sub(rd, rs, rt.rm());
}
} else if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
(rd != zero_reg) && is_int6(-rt.immediate()) &&
(rt.immediate() != 0) && !MustUseReg(rt.rmode())) {
c_addi(rd,
static_cast<int8_t>(
-rt.immediate())); // No c_subi instr, use c_addi(x, y, -imm).
} else if (v8_flags.riscv_c_extension && is_int10(-rt.immediate()) &&
(rt.immediate() != 0) && ((rt.immediate() & 0xf) == 0) &&
(rd.code() == rs.code()) && (rd == sp) &&
!MustUseReg(rt.rmode())) {
c_addi16sp(static_cast<int16_t>(-rt.immediate()));
} else if (is_int12(-rt.immediate()) && !MustUseReg(rt.rmode())) {
addi(rd, rs,
static_cast<int32_t>(
-rt.immediate())); // No subi instr, use addi(x, y, -imm).
} else if ((-4096 <= -rt.immediate() && -rt.immediate() <= -2049) ||
(2048 <= -rt.immediate() && -rt.immediate() <= 4094)) {
addi(rd, rs, -rt.immediate() / 2);
addi(rd, rd, -rt.immediate() - (-rt.immediate() / 2));
} else {
int li_count = InstrCountForLi64Bit(rt.immediate());
int li_neg_count = InstrCountForLi64Bit(-rt.immediate());
if (li_neg_count < li_count && !MustUseReg(rt.rmode())) {
// Use load -imm and add when loading -imm generates one instruction.
DCHECK(rt.immediate() != std::numeric_limits<int32_t>::min());
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
li(scratch, Operand(-rt.immediate()));
add(rd, rs, scratch);
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
li(scratch, rt);
sub(rd, rs, scratch);
}
}
}
void TurboAssembler::Add64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
(rt.rm() != zero_reg) && (rs != zero_reg)) {
c_add(rd, rt.rm());
} else {
add(rd, rs, rt.rm());
}
} else {
if (v8_flags.riscv_c_extension && is_int6(rt.immediate()) &&
(rd.code() == rs.code()) && (rd != zero_reg) && (rt.immediate() != 0) &&
!MustUseReg(rt.rmode())) {
c_addi(rd, static_cast<int8_t>(rt.immediate()));
} else if (v8_flags.riscv_c_extension && is_int10(rt.immediate()) &&
(rt.immediate() != 0) && ((rt.immediate() & 0xf) == 0) &&
(rd.code() == rs.code()) && (rd == sp) &&
!MustUseReg(rt.rmode())) {
c_addi16sp(static_cast<int16_t>(rt.immediate()));
} else if (v8_flags.riscv_c_extension &&
((rd.code() & 0b11000) == 0b01000) && (rs == sp) &&
is_uint10(rt.immediate()) && (rt.immediate() != 0) &&
!MustUseReg(rt.rmode())) {
c_addi4spn(rd, static_cast<uint16_t>(rt.immediate()));
} else if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) {
addi(rd, rs, static_cast<int32_t>(rt.immediate()));
} else if ((-4096 <= rt.immediate() && rt.immediate() <= -2049) ||
(2048 <= rt.immediate() && rt.immediate() <= 4094)) {
addi(rd, rs, rt.immediate() / 2);
addi(rd, rd, rt.immediate() - (rt.immediate() / 2));
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
BlockTrampolinePoolScope block_trampoline_pool(this);
li(scratch, rt);
add(rd, rs, scratch);
}
}
}
void TurboAssembler::Mul32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
mulw(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mulw(rd, rs, scratch);
}
}
void TurboAssembler::Mulh32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
mul(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mul(rd, rs, scratch);
}
srai(rd, rd, 32);
}
void TurboAssembler::Mulhu32(Register rd, Register rs, const Operand& rt,
Register rsz, Register rtz) {
slli(rsz, rs, 32);
if (rt.is_reg()) {
slli(rtz, rt.rm(), 32);
} else {
Li(rtz, rt.immediate() << 32);
}
mulhu(rd, rsz, rtz);
srai(rd, rd, 32);
}
void TurboAssembler::Mul64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
mul(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mul(rd, rs, scratch);
}
}
void TurboAssembler::Mulh64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
mulh(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mulh(rd, rs, scratch);
}
}
void TurboAssembler::Mulhu64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
mulhu(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mulhu(rd, rs, scratch);
}
}
void TurboAssembler::Div32(Register res, Register rs, const Operand& rt) {
if (rt.is_reg()) {
divw(res, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
divw(res, rs, scratch);
}
}
void TurboAssembler::Mod32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
remw(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
remw(rd, rs, scratch);
}
}
void TurboAssembler::Modu32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
remuw(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
remuw(rd, rs, scratch);
}
}
void TurboAssembler::Div64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
div(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
div(rd, rs, scratch);
}
}
void TurboAssembler::Divu32(Register res, Register rs, const Operand& rt) {
if (rt.is_reg()) {
divuw(res, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
divuw(res, rs, scratch);
}
}
void TurboAssembler::Divu64(Register res, Register rs, const Operand& rt) {
if (rt.is_reg()) {
divu(res, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
divu(res, rs, scratch);
}
}
void TurboAssembler::Mod64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
rem(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
rem(rd, rs, scratch);
}
}
void TurboAssembler::Modu64(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
remu(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
remu(rd, rs, scratch);
}
}
#elif V8_TARGET_ARCH_RISCV32
void TurboAssembler::AddWord(Register rd, Register rs, const Operand& rt) {
Add32(rd, rs, rt);
}
void TurboAssembler::Add32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
(rt.rm() != zero_reg) && (rs != zero_reg)) {
c_add(rd, rt.rm());
} else {
add(rd, rs, rt.rm());
}
} else {
if (v8_flags.riscv_c_extension && is_int6(rt.immediate()) &&
(rd.code() == rs.code()) && (rd != zero_reg) && (rt.immediate() != 0) &&
!MustUseReg(rt.rmode())) {
c_addi(rd, static_cast<int8_t>(rt.immediate()));
} else if (v8_flags.riscv_c_extension && is_int10(rt.immediate()) &&
(rt.immediate() != 0) && ((rt.immediate() & 0xf) == 0) &&
(rd.code() == rs.code()) && (rd == sp) &&
!MustUseReg(rt.rmode())) {
c_addi16sp(static_cast<int16_t>(rt.immediate()));
} else if (v8_flags.riscv_c_extension &&
((rd.code() & 0b11000) == 0b01000) && (rs == sp) &&
is_uint10(rt.immediate()) && (rt.immediate() != 0) &&
!MustUseReg(rt.rmode())) {
c_addi4spn(rd, static_cast<uint16_t>(rt.immediate()));
} else if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) {
addi(rd, rs, static_cast<int32_t>(rt.immediate()));
} else if ((-4096 <= rt.immediate() && rt.immediate() <= -2049) ||
(2048 <= rt.immediate() && rt.immediate() <= 4094)) {
addi(rd, rs, rt.immediate() / 2);
addi(rd, rd, rt.immediate() - (rt.immediate() / 2));
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
BlockTrampolinePoolScope block_trampoline_pool(this);
li(scratch, rt);
add(rd, rs, scratch);
}
}
}
void TurboAssembler::SubWord(Register rd, Register rs, const Operand& rt) {
Sub32(rd, rs, rt);
}
void TurboAssembler::Sub32(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
((rd.code() & 0b11000) == 0b01000) &&
((rt.rm().code() & 0b11000) == 0b01000)) {
c_sub(rd, rt.rm());
} else {
sub(rd, rs, rt.rm());
}
} else if (v8_flags.riscv_c_extension && (rd.code() == rs.code()) &&
(rd != zero_reg) && is_int6(-rt.immediate()) &&
(rt.immediate() != 0) && !MustUseReg(rt.rmode())) {
c_addi(rd,
static_cast<int8_t>(
-rt.immediate())); // No c_subi instr, use c_addi(x, y, -imm).
} else if (v8_flags.riscv_c_extension && is_int10(-rt.immediate()) &&
(rt.immediate() != 0) && ((rt.immediate() & 0xf) == 0) &&
(rd.code() == rs.code()) && (rd == sp) &&
!MustUseReg(rt.rmode())) {
c_addi16sp(static_cast<int16_t>(-rt.immediate()));
} else if (is_int12(-rt.immediate()) && !MustUseReg(rt.rmode())) {
addi(rd, rs,
static_cast<int32_t>(
-rt.immediate())); // No subi instr, use addi(x, y, -imm).
} else if ((-4096 <= -rt.immediate() && -rt.immediate() <= -2049) ||
(2048 <= -rt.immediate() && -rt.immediate() <= 4094)) {
addi(rd, rs, -rt.immediate() / 2);
addi(rd, rd, -rt.immediate() - (-rt.immediate() / 2));
} else {
// RV32G todo: imm64 or imm32 here
int li_count = InstrCountForLi64Bit(rt.immediate());
int li_neg_count = InstrCountForLi64Bit(-rt.immediate());
if (li_neg_count < li_count && !MustUseReg(rt.rmode())) {
// Use load -imm and add when loading -imm generates one instruction.
DCHECK(rt.immediate() != std::numeric_limits<int32_t>::min());
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
li(scratch, Operand(-rt.immediate()));
add(rd, rs, scratch);
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
li(scratch, rt);
sub(rd, rs, scratch);
}
}
}
void TurboAssembler::Mul32(Register rd, Register rs, const Operand& rt) {
Mul(rd, rs, rt);
}
void TurboAssembler::Mul(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
mul(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mul(rd, rs, scratch);
}
}
void TurboAssembler::Mulh(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
mulh(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mulh(rd, rs, scratch);
}
}
void TurboAssembler::Mulhu(Register rd, Register rs, const Operand& rt,
Register rsz, Register rtz) {
if (rt.is_reg()) {
mulhu(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
mulhu(rd, rs, scratch);
}
}
void TurboAssembler::Div(Register res, Register rs, const Operand& rt) {
if (rt.is_reg()) {
div(res, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
div(res, rs, scratch);
}
}
void TurboAssembler::Mod(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
rem(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
rem(rd, rs, scratch);
}
}
void TurboAssembler::Modu(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {
remu(rd, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
remu(rd, rs, scratch);
}
}
void TurboAssembler::Divu(Register res, Register rs, const Operand& rt) {
if (rt.is_reg()) {
divu(res, rs, rt.rm());
} else {
// li handles the relocation.
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
Li(scratch, rt.immediate());
divu(res, rs, scratch);
}
}
#endif
void TurboAssembler::And(Register rd, Register rs, const Operand& rt) {
if (rt.is_reg()) {