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constants-ppc.h
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constants-ppc.h
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// Copyright 2014 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef V8_CODEGEN_PPC_CONSTANTS_PPC_H_
#define V8_CODEGEN_PPC_CONSTANTS_PPC_H_
#include <stdint.h>
#include "src/base/logging.h"
#include "src/base/macros.h"
#include "src/common/globals.h"
// UNIMPLEMENTED_ macro for PPC.
#ifdef DEBUG
#define UNIMPLEMENTED_PPC() \
v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \
__FILE__, __LINE__, __func__)
#else
#define UNIMPLEMENTED_PPC()
#endif
#if V8_HOST_ARCH_PPC && \
(V8_OS_AIX || (V8_TARGET_ARCH_PPC64 && V8_TARGET_BIG_ENDIAN && \
(!defined(_CALL_ELF) || _CALL_ELF == 1)))
#define ABI_USES_FUNCTION_DESCRIPTORS 1
#else
#define ABI_USES_FUNCTION_DESCRIPTORS 0
#endif
#if !V8_HOST_ARCH_PPC || V8_OS_AIX || V8_TARGET_ARCH_PPC64
#define ABI_PASSES_HANDLES_IN_REGS 1
#else
#define ABI_PASSES_HANDLES_IN_REGS 0
#endif
#if !V8_HOST_ARCH_PPC || !V8_TARGET_ARCH_PPC64 || V8_TARGET_LITTLE_ENDIAN || \
(defined(_CALL_ELF) && _CALL_ELF == 2)
#define ABI_RETURNS_OBJECT_PAIRS_IN_REGS 1
#else
#define ABI_RETURNS_OBJECT_PAIRS_IN_REGS 0
#endif
#if !V8_HOST_ARCH_PPC || \
(V8_TARGET_ARCH_PPC64 && \
(V8_TARGET_LITTLE_ENDIAN || (defined(_CALL_ELF) && _CALL_ELF == 2)))
#define ABI_CALL_VIA_IP 1
#else
#define ABI_CALL_VIA_IP 0
#endif
#if !V8_HOST_ARCH_PPC || V8_OS_AIX || V8_TARGET_ARCH_PPC64
#define ABI_TOC_REGISTER 2
#else
#define ABI_TOC_REGISTER 13
#endif
namespace v8 {
namespace internal {
// TODO(sigurds): Change this value once we use relative jumps.
constexpr size_t kMaxPCRelativeCodeRangeInMB = 0;
// Used to encode a boolean value when emitting 32 bit
// opcodes which will indicate the presence of function descriptors
constexpr int kHasFunctionDescriptorBitShift = 9;
constexpr int kHasFunctionDescriptorBitMask = 1
<< kHasFunctionDescriptorBitShift;
// Number of registers
const int kNumRegisters = 32;
// FP support.
const int kNumDoubleRegisters = 32;
const int kNoRegister = -1;
// Used in embedded constant pool builder - max reach in bits for
// various load instructions (one less due to unsigned)
const int kLoadPtrMaxReachBits = 15;
const int kLoadDoubleMaxReachBits = 15;
// Actual value of root register is offset from the root array's start
// to take advantage of negative displacement values.
// TODO(sigurds): Choose best value.
constexpr int kRootRegisterBias = 128;
// sign-extend the least significant 16-bits of value <imm>
#define SIGN_EXT_IMM16(imm) ((static_cast<int>(imm) << 16) >> 16)
// sign-extend the least significant 22-bits of value <imm>
#define SIGN_EXT_IMM22(imm) ((static_cast<int>(imm) << 10) >> 10)
// sign-extend the least significant 26-bits of value <imm>
#define SIGN_EXT_IMM26(imm) ((static_cast<int>(imm) << 6) >> 6)
// -----------------------------------------------------------------------------
// Conditions.
// Defines constants and accessor classes to assemble, disassemble and
// simulate PPC instructions.
//
// Section references in the code refer to the "PowerPC Microprocessor
// Family: The Programmer.s Reference Guide" from 10/95
// https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF778525699600741775/$file/prg.pdf
//
// Constants for specific fields are defined in their respective named enums.
// General constants are in an anonymous enum in class Instr.
enum Condition {
kNoCondition = -1,
eq = 0, // Equal.
ne = 1, // Not equal.
ge = 2, // Greater or equal.
lt = 3, // Less than.
gt = 4, // Greater than.
le = 5, // Less then or equal
unordered = 6, // Floating-point unordered
ordered = 7,
overflow = 8, // Summary overflow
nooverflow = 9,
al = 10 // Always.
};
inline Condition NegateCondition(Condition cond) {
DCHECK(cond != al);
return static_cast<Condition>(cond ^ ne);
}
// -----------------------------------------------------------------------------
// Instructions encoding.
// Instr is merely used by the Assembler to distinguish 32bit integers
// representing instructions from usual 32 bit values.
// Instruction objects are pointers to 32bit values, and provide methods to
// access the various ISA fields.
using Instr = uint32_t;
#define PPC_XX3_OPCODE_LIST(V) \
/* VSX Scalar Add Double-Precision */ \
V(xsadddp, XSADDDP, 0xF0000100) \
/* VSX Scalar Add Single-Precision */ \
V(xsaddsp, XSADDSP, 0xF0000000) \
/* VSX Scalar Compare Ordered Double-Precision */ \
V(xscmpodp, XSCMPODP, 0xF0000158) \
/* VSX Scalar Compare Unordered Double-Precision */ \
V(xscmpudp, XSCMPUDP, 0xF0000118) \
/* VSX Scalar Copy Sign Double-Precision */ \
V(xscpsgndp, XSCPSGNDP, 0xF0000580) \
/* VSX Scalar Divide Double-Precision */ \
V(xsdivdp, XSDIVDP, 0xF00001C0) \
/* VSX Scalar Divide Single-Precision */ \
V(xsdivsp, XSDIVSP, 0xF00000C0) \
/* VSX Scalar Multiply-Add Type-A Double-Precision */ \
V(xsmaddadp, XSMADDADP, 0xF0000108) \
/* VSX Scalar Multiply-Add Type-A Single-Precision */ \
V(xsmaddasp, XSMADDASP, 0xF0000008) \
/* VSX Scalar Multiply-Add Type-M Double-Precision */ \
V(xsmaddmdp, XSMADDMDP, 0xF0000148) \
/* VSX Scalar Multiply-Add Type-M Single-Precision */ \
V(xsmaddmsp, XSMADDMSP, 0xF0000048) \
/* VSX Scalar Maximum Double-Precision */ \
V(xsmaxdp, XSMAXDP, 0xF0000500) \
/* VSX Scalar Minimum Double-Precision */ \
V(xsmindp, XSMINDP, 0xF0000540) \
/* VSX Scalar Multiply-Subtract Type-A Double-Precision */ \
V(xsmsubadp, XSMSUBADP, 0xF0000188) \
/* VSX Scalar Multiply-Subtract Type-A Single-Precision */ \
V(xsmsubasp, XSMSUBASP, 0xF0000088) \
/* VSX Scalar Multiply-Subtract Type-M Double-Precision */ \
V(xsmsubmdp, XSMSUBMDP, 0xF00001C8) \
/* VSX Scalar Multiply-Subtract Type-M Single-Precision */ \
V(xsmsubmsp, XSMSUBMSP, 0xF00000C8) \
/* VSX Scalar Multiply Double-Precision */ \
V(xsmuldp, XSMULDP, 0xF0000180) \
/* VSX Scalar Multiply Single-Precision */ \
V(xsmulsp, XSMULSP, 0xF0000080) \
/* VSX Scalar Negative Multiply-Add Type-A Double-Precision */ \
V(xsnmaddadp, XSNMADDADP, 0xF0000508) \
/* VSX Scalar Negative Multiply-Add Type-A Single-Precision */ \
V(xsnmaddasp, XSNMADDASP, 0xF0000408) \
/* VSX Scalar Negative Multiply-Add Type-M Double-Precision */ \
V(xsnmaddmdp, XSNMADDMDP, 0xF0000548) \
/* VSX Scalar Negative Multiply-Add Type-M Single-Precision */ \
V(xsnmaddmsp, XSNMADDMSP, 0xF0000448) \
/* VSX Scalar Negative Multiply-Subtract Type-A Double-Precision */ \
V(xsnmsubadp, XSNMSUBADP, 0xF0000588) \
/* VSX Scalar Negative Multiply-Subtract Type-A Single-Precision */ \
V(xsnmsubasp, XSNMSUBASP, 0xF0000488) \
/* VSX Scalar Negative Multiply-Subtract Type-M Double-Precision */ \
V(xsnmsubmdp, XSNMSUBMDP, 0xF00005C8) \
/* VSX Scalar Negative Multiply-Subtract Type-M Single-Precision */ \
V(xsnmsubmsp, XSNMSUBMSP, 0xF00004C8) \
/* VSX Scalar Reciprocal Estimate Double-Precision */ \
V(xsredp, XSREDP, 0xF0000168) \
/* VSX Scalar Reciprocal Estimate Single-Precision */ \
V(xsresp, XSRESP, 0xF0000068) \
/* VSX Scalar Subtract Double-Precision */ \
V(xssubdp, XSSUBDP, 0xF0000140) \
/* VSX Scalar Subtract Single-Precision */ \
V(xssubsp, XSSUBSP, 0xF0000040) \
/* VSX Scalar Test for software Divide Double-Precision */ \
V(xstdivdp, XSTDIVDP, 0xF00001E8) \
/* VSX Vector Add Double-Precision */ \
V(xvadddp, XVADDDP, 0xF0000300) \
/* VSX Vector Add Single-Precision */ \
V(xvaddsp, XVADDSP, 0xF0000200) \
/* VSX Vector Compare Equal To Double-Precision */ \
V(xvcmpeqdp, XVCMPEQDP, 0xF0000318) \
/* VSX Vector Compare Equal To Double-Precision & record CR6 */ \
V(xvcmpeqdpx, XVCMPEQDPx, 0xF0000718) \
/* VSX Vector Compare Equal To Single-Precision */ \
V(xvcmpeqsp, XVCMPEQSP, 0xF0000218) \
/* VSX Vector Compare Equal To Single-Precision & record CR6 */ \
V(xvcmpeqspx, XVCMPEQSPx, 0xF0000618) \
/* VSX Vector Compare Greater Than or Equal To Double-Precision */ \
V(xvcmpgedp, XVCMPGEDP, 0xF0000398) \
/* VSX Vector Compare Greater Than or Equal To Double-Precision & record */ \
/* CR6 */ \
V(xvcmpgedpx, XVCMPGEDPx, 0xF0000798) \
/* VSX Vector Compare Greater Than or Equal To Single-Precision */ \
V(xvcmpgesp, XVCMPGESP, 0xF0000298) \
/* VSX Vector Compare Greater Than or Equal To Single-Precision & record */ \
/* CR6 */ \
V(xvcmpgespx, XVCMPGESPx, 0xF0000698) \
/* VSX Vector Compare Greater Than Double-Precision */ \
V(xvcmpgtdp, XVCMPGTDP, 0xF0000358) \
/* VSX Vector Compare Greater Than Double-Precision & record CR6 */ \
V(xvcmpgtdpx, XVCMPGTDPx, 0xF0000758) \
/* VSX Vector Compare Greater Than Single-Precision */ \
V(xvcmpgtsp, XVCMPGTSP, 0xF0000258) \
/* VSX Vector Compare Greater Than Single-Precision & record CR6 */ \
V(xvcmpgtspx, XVCMPGTSPx, 0xF0000658) \
/* VSX Vector Copy Sign Double-Precision */ \
V(xvcpsgndp, XVCPSGNDP, 0xF0000780) \
/* VSX Vector Copy Sign Single-Precision */ \
V(xvcpsgnsp, XVCPSGNSP, 0xF0000680) \
/* VSX Vector Divide Double-Precision */ \
V(xvdivdp, XVDIVDP, 0xF00003C0) \
/* VSX Vector Divide Single-Precision */ \
V(xvdivsp, XVDIVSP, 0xF00002C0) \
/* VSX Vector Multiply-Add Type-A Double-Precision */ \
V(xvmaddadp, XVMADDADP, 0xF0000308) \
/* VSX Vector Multiply-Add Type-A Single-Precision */ \
V(xvmaddasp, XVMADDASP, 0xF0000208) \
/* VSX Vector Multiply-Add Type-M Double-Precision */ \
V(xvmaddmdp, XVMADDMDP, 0xF0000348) \
/* VSX Vector Multiply-Add Type-M Single-Precision */ \
V(xvmaddmsp, XVMADDMSP, 0xF0000248) \
/* VSX Vector Maximum Double-Precision */ \
V(xvmaxdp, XVMAXDP, 0xF0000700) \
/* VSX Vector Maximum Single-Precision */ \
V(xvmaxsp, XVMAXSP, 0xF0000600) \
/* VSX Vector Minimum Double-Precision */ \
V(xvmindp, XVMINDP, 0xF0000740) \
/* VSX Vector Minimum Single-Precision */ \
V(xvminsp, XVMINSP, 0xF0000640) \
/* VSX Vector Multiply-Subtract Type-A Double-Precision */ \
V(xvmsubadp, XVMSUBADP, 0xF0000388) \
/* VSX Vector Multiply-Subtract Type-A Single-Precision */ \
V(xvmsubasp, XVMSUBASP, 0xF0000288) \
/* VSX Vector Multiply-Subtract Type-M Double-Precision */ \
V(xvmsubmdp, XVMSUBMDP, 0xF00003C8) \
/* VSX Vector Multiply-Subtract Type-M Single-Precision */ \
V(xvmsubmsp, XVMSUBMSP, 0xF00002C8) \
/* VSX Vector Multiply Double-Precision */ \
V(xvmuldp, XVMULDP, 0xF0000380) \
/* VSX Vector Multiply Single-Precision */ \
V(xvmulsp, XVMULSP, 0xF0000280) \
/* VSX Vector Negative Multiply-Add Type-A Double-Precision */ \
V(xvnmaddadp, XVNMADDADP, 0xF0000708) \
/* VSX Vector Negative Multiply-Add Type-A Single-Precision */ \
V(xvnmaddasp, XVNMADDASP, 0xF0000608) \
/* VSX Vector Negative Multiply-Add Type-M Double-Precision */ \
V(xvnmaddmdp, XVNMADDMDP, 0xF0000748) \
/* VSX Vector Negative Multiply-Add Type-M Single-Precision */ \
V(xvnmaddmsp, XVNMADDMSP, 0xF0000648) \
/* VSX Vector Negative Multiply-Subtract Type-A Double-Precision */ \
V(xvnmsubadp, XVNMSUBADP, 0xF0000788) \
/* VSX Vector Negative Multiply-Subtract Type-A Single-Precision */ \
V(xvnmsubasp, XVNMSUBASP, 0xF0000688) \
/* VSX Vector Negative Multiply-Subtract Type-M Double-Precision */ \
V(xvnmsubmdp, XVNMSUBMDP, 0xF00007C8) \
/* VSX Vector Negative Multiply-Subtract Type-M Single-Precision */ \
V(xvnmsubmsp, XVNMSUBMSP, 0xF00006C8) \
/* VSX Vector Reciprocal Estimate Double-Precision */ \
V(xvredp, XVREDP, 0xF0000368) \
/* VSX Vector Reciprocal Estimate Single-Precision */ \
V(xvresp, XVRESP, 0xF0000268) \
/* VSX Vector Subtract Double-Precision */ \
V(xvsubdp, XVSUBDP, 0xF0000340) \
/* VSX Vector Subtract Single-Precision */ \
V(xvsubsp, XVSUBSP, 0xF0000240) \
/* VSX Vector Test for software Divide Double-Precision */ \
V(xvtdivdp, XVTDIVDP, 0xF00003E8) \
/* VSX Vector Test for software Divide Single-Precision */ \
V(xvtdivsp, XVTDIVSP, 0xF00002E8) \
/* VSX Logical AND */ \
V(xxland, XXLAND, 0xF0000410) \
/* VSX Logical AND with Complement */ \
V(xxlandc, XXLANDC, 0xF0000450) \
/* VSX Logical Equivalence */ \
V(xxleqv, XXLEQV, 0xF00005D0) \
/* VSX Logical NAND */ \
V(xxlnand, XXLNAND, 0xF0000590) \
/* VSX Logical NOR */ \
V(xxlnor, XXLNOR, 0xF0000510) \
/* VSX Logical OR */ \
V(xxlor, XXLOR, 0xF0000490) \
/* VSX Logical OR with Complement */ \
V(xxlorc, XXLORC, 0xF0000550) \
/* VSX Logical XOR */ \
V(xxlxor, XXLXOR, 0xF00004D0) \
/* VSX Merge High Word */ \
V(xxmrghw, XXMRGHW, 0xF0000090) \
/* VSX Merge Low Word */ \
V(xxmrglw, XXMRGLW, 0xF0000190) \
/* VSX Permute Doubleword Immediate */ \
V(xxpermdi, XXPERMDI, 0xF0000050) \
/* VSX Shift Left Double by Word Immediate */ \
V(xxsldwi, XXSLDWI, 0xF0000010) \
/* VSX Splat Word */ \
V(xxspltw, XXSPLTW, 0xF0000290)
#define PPC_Z23_OPCODE_LIST(V) \
/* Decimal Quantize */ \
V(dqua, DQUA, 0xEC000006) \
/* Decimal Quantize Immediate */ \
V(dquai, DQUAI, 0xEC000086) \
/* Decimal Quantize Immediate Quad */ \
V(dquaiq, DQUAIQ, 0xFC000086) \
/* Decimal Quantize Quad */ \
V(dquaq, DQUAQ, 0xFC000006) \
/* Decimal Floating Round To FP Integer Without Inexact */ \
V(drintn, DRINTN, 0xEC0001C6) \
/* Decimal Floating Round To FP Integer Without Inexact Quad */ \
V(drintnq, DRINTNQ, 0xFC0001C6) \
/* Decimal Floating Round To FP Integer With Inexact */ \
V(drintx, DRINTX, 0xEC0000C6) \
/* Decimal Floating Round To FP Integer With Inexact Quad */ \
V(drintxq, DRINTXQ, 0xFC0000C6) \
/* Decimal Floating Reround */ \
V(drrnd, DRRND, 0xEC000046) \
/* Decimal Floating Reround Quad */ \
V(drrndq, DRRNDQ, 0xFC000046)
#define PPC_Z22_OPCODE_LIST(V) \
/* Decimal Floating Shift Coefficient Left Immediate */ \
V(dscli, DSCLI, 0xEC000084) \
/* Decimal Floating Shift Coefficient Left Immediate Quad */ \
V(dscliq, DSCLIQ, 0xFC000084) \
/* Decimal Floating Shift Coefficient Right Immediate */ \
V(dscri, DSCRI, 0xEC0000C4) \
/* Decimal Floating Shift Coefficient Right Immediate Quad */ \
V(dscriq, DSCRIQ, 0xFC0000C4) \
/* Decimal Floating Test Data Class */ \
V(dtstdc, DTSTDC, 0xEC000184) \
/* Decimal Floating Test Data Class Quad */ \
V(dtstdcq, DTSTDCQ, 0xFC000184) \
/* Decimal Floating Test Data Group */ \
V(dtstdg, DTSTDG, 0xEC0001C4) \
/* Decimal Floating Test Data Group Quad */ \
V(dtstdgq, DTSTDGQ, 0xFC0001C4)
#define PPC_XX2_OPCODE_LIST(V) \
/* Move To VSR Doubleword */ \
V(mtvsrd, MTVSRD, 0x7C000166) \
/* Move To VSR Word Algebraic */ \
V(mtvsrwa, MTVSRWA, 0x7C0001A6) \
/* Move To VSR Word and Zero */ \
V(mtvsrwz, MTVSRWZ, 0x7C0001E6) \
/* VSX Scalar Absolute Value Double-Precision */ \
V(xsabsdp, XSABSDP, 0xF0000564) \
/* VSX Scalar Convert Double-Precision to Single-Precision */ \
V(xscvdpsp, XSCVDPSP, 0xF0000424) \
/* VSX Scalar Convert Double-Precision to Single-Precision format Non- */ \
/* signalling */ \
V(xscvdpspn, XSCVDPSPN, 0xF000042C) \
/* VSX Scalar Convert Double-Precision to Signed Fixed-Point Doubleword */ \
/* Saturate */ \
V(xscvdpsxds, XSCVDPSXDS, 0xF0000560) \
/* VSX Scalar Convert Double-Precision to Signed Fixed-Point Word */ \
/* Saturate */ \
V(xscvdpsxws, XSCVDPSXWS, 0xF0000160) \
/* VSX Scalar Convert Double-Precision to Unsigned Fixed-Point */ \
/* Doubleword Saturate */ \
V(xscvdpuxds, XSCVDPUXDS, 0xF0000520) \
/* VSX Scalar Convert Double-Precision to Unsigned Fixed-Point Word */ \
/* Saturate */ \
V(xscvdpuxws, XSCVDPUXWS, 0xF0000120) \
/* VSX Scalar Convert Single-Precision to Double-Precision (p=1) */ \
V(xscvspdp, XSCVSPDP, 0xF0000524) \
/* Scalar Convert Single-Precision to Double-Precision format Non- */ \
/* signalling */ \
V(xscvspdpn, XSCVSPDPN, 0xF000052C) \
/* VSX Scalar Convert Signed Fixed-Point Doubleword to Double-Precision */ \
V(xscvsxddp, XSCVSXDDP, 0xF00005E0) \
/* VSX Scalar Convert Signed Fixed-Point Doubleword to Single-Precision */ \
V(xscvsxdsp, XSCVSXDSP, 0xF00004E0) \
/* VSX Scalar Convert Unsigned Fixed-Point Doubleword to Double- */ \
/* Precision */ \
V(xscvuxddp, XSCVUXDDP, 0xF00005A0) \
/* VSX Scalar Convert Unsigned Fixed-Point Doubleword to Single- */ \
/* Precision */ \
V(xscvuxdsp, XSCVUXDSP, 0xF00004A0) \
/* VSX Scalar Negative Absolute Value Double-Precision */ \
V(xsnabsdp, XSNABSDP, 0xF00005A4) \
/* VSX Scalar Negate Double-Precision */ \
V(xsnegdp, XSNEGDP, 0xF00005E4) \
/* VSX Scalar Round to Double-Precision Integer */ \
V(xsrdpi, XSRDPI, 0xF0000124) \
/* VSX Scalar Round to Double-Precision Integer using Current rounding */ \
/* mode */ \
V(xsrdpic, XSRDPIC, 0xF00001AC) \
/* VSX Scalar Round to Double-Precision Integer toward -Infinity */ \
V(xsrdpim, XSRDPIM, 0xF00001E4) \
/* VSX Scalar Round to Double-Precision Integer toward +Infinity */ \
V(xsrdpip, XSRDPIP, 0xF00001A4) \
/* VSX Scalar Round to Double-Precision Integer toward Zero */ \
V(xsrdpiz, XSRDPIZ, 0xF0000164) \
/* VSX Scalar Round to Single-Precision */ \
V(xsrsp, XSRSP, 0xF0000464) \
/* VSX Scalar Reciprocal Square Root Estimate Double-Precision */ \
V(xsrsqrtedp, XSRSQRTEDP, 0xF0000128) \
/* VSX Scalar Reciprocal Square Root Estimate Single-Precision */ \
V(xsrsqrtesp, XSRSQRTESP, 0xF0000028) \
/* VSX Scalar Square Root Double-Precision */ \
V(xssqrtdp, XSSQRTDP, 0xF000012C) \
/* VSX Scalar Square Root Single-Precision */ \
V(xssqrtsp, XSSQRTSP, 0xF000002C) \
/* VSX Scalar Test for software Square Root Double-Precision */ \
V(xstsqrtdp, XSTSQRTDP, 0xF00001A8) \
/* VSX Vector Absolute Value Double-Precision */ \
V(xvabsdp, XVABSDP, 0xF0000764) \
/* VSX Vector Absolute Value Single-Precision */ \
V(xvabssp, XVABSSP, 0xF0000664) \
/* VSX Vector Convert Double-Precision to Single-Precision */ \
V(xvcvdpsp, XVCVDPSP, 0xF0000624) \
/* VSX Vector Convert Double-Precision to Signed Fixed-Point Doubleword */ \
/* Saturate */ \
V(xvcvdpsxds, XVCVDPSXDS, 0xF0000760) \
/* VSX Vector Convert Double-Precision to Signed Fixed-Point Word */ \
/* Saturate */ \
V(xvcvdpsxws, XVCVDPSXWS, 0xF0000360) \
/* VSX Vector Convert Double-Precision to Unsigned Fixed-Point */ \
/* Doubleword Saturate */ \
V(xvcvdpuxds, XVCVDPUXDS, 0xF0000720) \
/* VSX Vector Convert Double-Precision to Unsigned Fixed-Point Word */ \
/* Saturate */ \
V(xvcvdpuxws, XVCVDPUXWS, 0xF0000320) \
/* VSX Vector Convert Single-Precision to Double-Precision */ \
V(xvcvspdp, XVCVSPDP, 0xF0000724) \
/* VSX Vector Convert Single-Precision to Signed Fixed-Point Doubleword */ \
/* Saturate */ \
V(xvcvspsxds, XVCVSPSXDS, 0xF0000660) \
/* VSX Vector Convert Single-Precision to Signed Fixed-Point Word */ \
/* Saturate */ \
V(xvcvspsxws, XVCVSPSXWS, 0xF0000260) \
/* VSX Vector Convert Single-Precision to Unsigned Fixed-Point */ \
/* Doubleword Saturate */ \
V(xvcvspuxds, XVCVSPUXDS, 0xF0000620) \
/* VSX Vector Convert Single-Precision to Unsigned Fixed-Point Word */ \
/* Saturate */ \
V(xvcvspuxws, XVCVSPUXWS, 0xF0000220) \
/* VSX Vector Convert Signed Fixed-Point Doubleword to Double-Precision */ \
V(xvcvsxddp, XVCVSXDDP, 0xF00007E0) \
/* VSX Vector Convert Signed Fixed-Point Doubleword to Single-Precision */ \
V(xvcvsxdsp, XVCVSXDSP, 0xF00006E0) \
/* VSX Vector Convert Signed Fixed-Point Word to Double-Precision */ \
V(xvcvsxwdp, XVCVSXWDP, 0xF00003E0) \
/* VSX Vector Convert Signed Fixed-Point Word to Single-Precision */ \
V(xvcvsxwsp, XVCVSXWSP, 0xF00002E0) \
/* VSX Vector Convert Unsigned Fixed-Point Doubleword to Double- */ \
/* Precision */ \
V(xvcvuxddp, XVCVUXDDP, 0xF00007A0) \
/* VSX Vector Convert Unsigned Fixed-Point Doubleword to Single- */ \
/* Precision */ \
V(xvcvuxdsp, XVCVUXDSP, 0xF00006A0) \
/* VSX Vector Convert Unsigned Fixed-Point Word to Double-Precision */ \
V(xvcvuxwdp, XVCVUXWDP, 0xF00003A0) \
/* VSX Vector Convert Unsigned Fixed-Point Word to Single-Precision */ \
V(xvcvuxwsp, XVCVUXWSP, 0xF00002A0) \
/* VSX Vector Negative Absolute Value Double-Precision */ \
V(xvnabsdp, XVNABSDP, 0xF00007A4) \
/* VSX Vector Negative Absolute Value Single-Precision */ \
V(xvnabssp, XVNABSSP, 0xF00006A4) \
/* VSX Vector Negate Double-Precision */ \
V(xvnegdp, XVNEGDP, 0xF00007E4) \
/* VSX Vector Negate Single-Precision */ \
V(xvnegsp, XVNEGSP, 0xF00006E4) \
/* VSX Vector Round to Double-Precision Integer */ \
V(xvrdpi, XVRDPI, 0xF0000324) \
/* VSX Vector Round to Double-Precision Integer using Current rounding */ \
/* mode */ \
V(xvrdpic, XVRDPIC, 0xF00003AC) \
/* VSX Vector Round to Double-Precision Integer toward -Infinity */ \
V(xvrdpim, XVRDPIM, 0xF00003E4) \
/* VSX Vector Round to Double-Precision Integer toward +Infinity */ \
V(xvrdpip, XVRDPIP, 0xF00003A4) \
/* VSX Vector Round to Double-Precision Integer toward Zero */ \
V(xvrdpiz, XVRDPIZ, 0xF0000364) \
/* VSX Vector Round to Single-Precision Integer */ \
V(xvrspi, XVRSPI, 0xF0000224) \
/* VSX Vector Round to Single-Precision Integer using Current rounding */ \
/* mode */ \
V(xvrspic, XVRSPIC, 0xF00002AC) \
/* VSX Vector Round to Single-Precision Integer toward -Infinity */ \
V(xvrspim, XVRSPIM, 0xF00002E4) \
/* VSX Vector Round to Single-Precision Integer toward +Infinity */ \
V(xvrspip, XVRSPIP, 0xF00002A4) \
/* VSX Vector Round to Single-Precision Integer toward Zero */ \
V(xvrspiz, XVRSPIZ, 0xF0000264) \
/* VSX Vector Reciprocal Square Root Estimate Double-Precision */ \
V(xvrsqrtedp, XVRSQRTEDP, 0xF0000328) \
/* VSX Vector Reciprocal Square Root Estimate Single-Precision */ \
V(xvrsqrtesp, XVRSQRTESP, 0xF0000228) \
/* VSX Vector Square Root Double-Precision */ \
V(xvsqrtdp, XVSQRTDP, 0xF000032C) \
/* VSX Vector Square Root Single-Precision */ \
V(xvsqrtsp, XVSQRTSP, 0xF000022C) \
/* VSX Vector Test for software Square Root Double-Precision */ \
V(xvtsqrtdp, XVTSQRTDP, 0xF00003A8) \
/* VSX Vector Test for software Square Root Single-Precision */ \
V(xvtsqrtsp, XVTSQRTSP, 0xF00002A8)
#define PPC_EVX_OPCODE_LIST(V) \
/* Vector Load Double Word into Double Word by External PID Indexed */ \
V(evlddepx, EVLDDEPX, 0x7C00063E) \
/* Vector Store Double of Double by External PID Indexed */ \
V(evstddepx, EVSTDDEPX, 0x7C00073E) \
/* Bit Reversed Increment */ \
V(brinc, BRINC, 0x1000020F) \
/* Vector Absolute Value */ \
V(evabs, EVABS, 0x10000208) \
/* Vector Add Immediate Word */ \
V(evaddiw, EVADDIW, 0x10000202) \
/* Vector Add Signed, Modulo, Integer to Accumulator Word */ \
V(evaddsmiaaw, EVADDSMIAAW, 0x100004C9) \
/* Vector Add Signed, Saturate, Integer to Accumulator Word */ \
V(evaddssiaaw, EVADDSSIAAW, 0x100004C1) \
/* Vector Add Unsigned, Modulo, Integer to Accumulator Word */ \
V(evaddumiaaw, EVADDUMIAAW, 0x100004C8) \
/* Vector Add Unsigned, Saturate, Integer to Accumulator Word */ \
V(evaddusiaaw, EVADDUSIAAW, 0x100004C0) \
/* Vector Add Word */ \
V(evaddw, EVADDW, 0x10000200) \
/* Vector AND */ \
V(evand, EVAND, 0x10000211) \
/* Vector AND with Complement */ \
V(evandc, EVANDC, 0x10000212) \
/* Vector Compare Equal */ \
V(evcmpeq, EVCMPEQ, 0x10000234) \
/* Vector Compare Greater Than Signed */ \
V(evcmpgts, EVCMPGTS, 0x10000231) \
/* Vector Compare Greater Than Unsigned */ \
V(evcmpgtu, EVCMPGTU, 0x10000230) \
/* Vector Compare Less Than Signed */ \
V(evcmplts, EVCMPLTS, 0x10000233) \
/* Vector Compare Less Than Unsigned */ \
V(evcmpltu, EVCMPLTU, 0x10000232) \
/* Vector Count Leading Signed Bits Word */ \
V(evcntlsw, EVCNTLSW, 0x1000020E) \
/* Vector Count Leading Zeros Word */ \
V(evcntlzw, EVCNTLZW, 0x1000020D) \
/* Vector Divide Word Signed */ \
V(evdivws, EVDIVWS, 0x100004C6) \
/* Vector Divide Word Unsigned */ \
V(evdivwu, EVDIVWU, 0x100004C7) \
/* Vector Equivalent */ \
V(eveqv, EVEQV, 0x10000219) \
/* Vector Extend Sign Byte */ \
V(evextsb, EVEXTSB, 0x1000020A) \
/* Vector Extend Sign Half Word */ \
V(evextsh, EVEXTSH, 0x1000020B) \
/* Vector Load Double Word into Double Word */ \
V(evldd, EVLDD, 0x10000301) \
/* Vector Load Double Word into Double Word Indexed */ \
V(evlddx, EVLDDX, 0x10000300) \
/* Vector Load Double into Four Half Words */ \
V(evldh, EVLDH, 0x10000305) \
/* Vector Load Double into Four Half Words Indexed */ \
V(evldhx, EVLDHX, 0x10000304) \
/* Vector Load Double into Two Words */ \
V(evldw, EVLDW, 0x10000303) \
/* Vector Load Double into Two Words Indexed */ \
V(evldwx, EVLDWX, 0x10000302) \
/* Vector Load Half Word into Half Words Even and Splat */ \
V(evlhhesplat, EVLHHESPLAT, 0x10000309) \
/* Vector Load Half Word into Half Words Even and Splat Indexed */ \
V(evlhhesplatx, EVLHHESPLATX, 0x10000308) \
/* Vector Load Half Word into Half Word Odd Signed and Splat */ \
V(evlhhossplat, EVLHHOSSPLAT, 0x1000030F) \
/* Vector Load Half Word into Half Word Odd Signed and Splat Indexed */ \
V(evlhhossplatx, EVLHHOSSPLATX, 0x1000030E) \
/* Vector Load Half Word into Half Word Odd Unsigned and Splat */ \
V(evlhhousplat, EVLHHOUSPLAT, 0x1000030D) \
/* Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed */ \
V(evlhhousplatx, EVLHHOUSPLATX, 0x1000030C) \
/* Vector Load Word into Two Half Words Even */ \
V(evlwhe, EVLWHE, 0x10000311) \
/* Vector Load Word into Two Half Words Odd Signed (with sign extension) */ \
V(evlwhos, EVLWHOS, 0x10000317) \
/* Vector Load Word into Two Half Words Odd Signed Indexed (with sign */ \
/* extension) */ \
V(evlwhosx, EVLWHOSX, 0x10000316) \
/* Vector Load Word into Two Half Words Odd Unsigned (zero-extended) */ \
V(evlwhou, EVLWHOU, 0x10000315) \
/* Vector Load Word into Two Half Words Odd Unsigned Indexed (zero- */ \
/* extended) */ \
V(evlwhoux, EVLWHOUX, 0x10000314) \
/* Vector Load Word into Two Half Words and Splat */ \
V(evlwhsplat, EVLWHSPLAT, 0x1000031D) \
/* Vector Load Word into Two Half Words and Splat Indexed */ \
V(evlwhsplatx, EVLWHSPLATX, 0x1000031C) \
/* Vector Load Word into Word and Splat */ \
V(evlwwsplat, EVLWWSPLAT, 0x10000319) \
/* Vector Load Word into Word and Splat Indexed */ \
V(evlwwsplatx, EVLWWSPLATX, 0x10000318) \
/* Vector Merge High */ \
V(evmergehi, EVMERGEHI, 0x1000022C) \
/* Vector Merge High/Low */ \
V(evmergehilo, EVMERGEHILO, 0x1000022E) \
/* Vector Merge Low */ \
V(evmergelo, EVMERGELO, 0x1000022D) \
/* Vector Merge Low/High */ \
V(evmergelohi, EVMERGELOHI, 0x1000022F) \
/* Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional */ \
/* and Accumulate */ \
V(evmhegsmfaa, EVMHEGSMFAA, 0x1000052B) \
/* Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional */ \
/* and Accumulate Negative */ \
V(evmhegsmfan, EVMHEGSMFAN, 0x100005AB) \
/* Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Integer */ \
/* and Accumulate */ \
V(evmhegsmiaa, EVMHEGSMIAA, 0x10000529) \
/* Vector Multiply Half Words, Even, Guarded, Signed, Modulo, Integer */ \
/* and Accumulate Negative */ \
V(evmhegsmian, EVMHEGSMIAN, 0x100005A9) \
/* Vector Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer */ \
/* and Accumulate */ \
V(evmhegumiaa, EVMHEGUMIAA, 0x10000528) \
/* Vector Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer */ \
/* and Accumulate Negative */ \
V(evmhegumian, EVMHEGUMIAN, 0x100005A8) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Fractional */ \
V(evmhesmf, EVMHESMF, 0x1000040B) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Fractional to */ \
/* Accumulator */ \
V(evmhesmfa, EVMHESMFA, 0x1000042B) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Fractional and */ \
/* Accumulate into Words */ \
V(evmhesmfaaw, EVMHESMFAAW, 0x1000050B) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Fractional and */ \
/* Accumulate Negative into Words */ \
V(evmhesmfanw, EVMHESMFANW, 0x1000058B) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Integer */ \
V(evmhesmi, EVMHESMI, 0x10000409) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Integer to */ \
/* Accumulator */ \
V(evmhesmia, EVMHESMIA, 0x10000429) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Integer and */ \
/* Accumulate into Words */ \
V(evmhesmiaaw, EVMHESMIAAW, 0x10000509) \
/* Vector Multiply Half Words, Even, Signed, Modulo, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmhesmianw, EVMHESMIANW, 0x10000589) \
/* Vector Multiply Half Words, Even, Signed, Saturate, Fractional */ \
V(evmhessf, EVMHESSF, 0x10000403) \
/* Vector Multiply Half Words, Even, Signed, Saturate, Fractional to */ \
/* Accumulator */ \
V(evmhessfa, EVMHESSFA, 0x10000423) \
/* Vector Multiply Half Words, Even, Signed, Saturate, Fractional and */ \
/* Accumulate into Words */ \
V(evmhessfaaw, EVMHESSFAAW, 0x10000503) \
/* Vector Multiply Half Words, Even, Signed, Saturate, Fractional and */ \
/* Accumulate Negative into Words */ \
V(evmhessfanw, EVMHESSFANW, 0x10000583) \
/* Vector Multiply Half Words, Even, Signed, Saturate, Integer and */ \
/* Accumulate into Words */ \
V(evmhessiaaw, EVMHESSIAAW, 0x10000501) \
/* Vector Multiply Half Words, Even, Signed, Saturate, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmhessianw, EVMHESSIANW, 0x10000581) \
/* Vector Multiply Half Words, Even, Unsigned, Modulo, Integer */ \
V(evmheumi, EVMHEUMI, 0x10000408) \
/* Vector Multiply Half Words, Even, Unsigned, Modulo, Integer to */ \
/* Accumulator */ \
V(evmheumia, EVMHEUMIA, 0x10000428) \
/* Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and */ \
/* Accumulate into Words */ \
V(evmheumiaaw, EVMHEUMIAAW, 0x10000508) \
/* Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmheumianw, EVMHEUMIANW, 0x10000588) \
/* Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and */ \
/* Accumulate into Words */ \
V(evmheusiaaw, EVMHEUSIAAW, 0x10000500) \
/* Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmheusianw, EVMHEUSIANW, 0x10000580) \
/* Vector Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional */ \
/* and Accumulate */ \
V(evmhogsmfaa, EVMHOGSMFAA, 0x1000052F) \
/* Vector Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional */ \
/* and Accumulate Negative */ \
V(evmhogsmfan, EVMHOGSMFAN, 0x100005AF) \
/* Vector Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer, */ \
/* and Accumulate */ \
V(evmhogsmiaa, EVMHOGSMIAA, 0x1000052D) \
/* Vector Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and */ \
/* Accumulate Negative */ \
V(evmhogsmian, EVMHOGSMIAN, 0x100005AD) \
/* Vector Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer */ \
/* and Accumulate */ \
V(evmhogumiaa, EVMHOGUMIAA, 0x1000052C) \
/* Vector Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer */ \
/* and Accumulate Negative */ \
V(evmhogumian, EVMHOGUMIAN, 0x100005AC) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Fractional */ \
V(evmhosmf, EVMHOSMF, 0x1000040F) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Fractional to */ \
/* Accumulator */ \
V(evmhosmfa, EVMHOSMFA, 0x1000042F) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and */ \
/* Accumulate into Words */ \
V(evmhosmfaaw, EVMHOSMFAAW, 0x1000050F) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and */ \
/* Accumulate Negative into Words */ \
V(evmhosmfanw, EVMHOSMFANW, 0x1000058F) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Integer */ \
V(evmhosmi, EVMHOSMI, 0x1000040D) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Integer to */ \
/* Accumulator */ \
V(evmhosmia, EVMHOSMIA, 0x1000042D) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Integer and */ \
/* Accumulate into Words */ \
V(evmhosmiaaw, EVMHOSMIAAW, 0x1000050D) \
/* Vector Multiply Half Words, Odd, Signed, Modulo, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmhosmianw, EVMHOSMIANW, 0x1000058D) \
/* Vector Multiply Half Words, Odd, Signed, Saturate, Fractional */ \
V(evmhossf, EVMHOSSF, 0x10000407) \
/* Vector Multiply Half Words, Odd, Signed, Saturate, Fractional to */ \
/* Accumulator */ \
V(evmhossfa, EVMHOSSFA, 0x10000427) \
/* Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and */ \
/* Accumulate into Words */ \
V(evmhossfaaw, EVMHOSSFAAW, 0x10000507) \
/* Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and */ \
/* Accumulate Negative into Words */ \
V(evmhossfanw, EVMHOSSFANW, 0x10000587) \
/* Vector Multiply Half Words, Odd, Signed, Saturate, Integer and */ \
/* Accumulate into Words */ \
V(evmhossiaaw, EVMHOSSIAAW, 0x10000505) \
/* Vector Multiply Half Words, Odd, Signed, Saturate, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmhossianw, EVMHOSSIANW, 0x10000585) \
/* Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer */ \
V(evmhoumi, EVMHOUMI, 0x1000040C) \
/* Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer to */ \
/* Accumulator */ \
V(evmhoumia, EVMHOUMIA, 0x1000042C) \
/* Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and */ \
/* Accumulate into Words */ \
V(evmhoumiaaw, EVMHOUMIAAW, 0x1000050C) \
/* Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmhoumianw, EVMHOUMIANW, 0x1000058C) \
/* Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and */ \
/* Accumulate into Words */ \
V(evmhousiaaw, EVMHOUSIAAW, 0x10000504) \
/* Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and */ \
/* Accumulate Negative into Words */ \
V(evmhousianw, EVMHOUSIANW, 0x10000584) \
/* Initialize Accumulator */ \
V(evmra, EVMRA, 0x100004C4) \
/* Vector Multiply Word High Signed, Modulo, Fractional */ \
V(evmwhsmf, EVMWHSMF, 0x1000044F) \
/* Vector Multiply Word High Signed, Modulo, Fractional to Accumulator */ \
V(evmwhsmfa, EVMWHSMFA, 0x1000046F) \
/* Vector Multiply Word High Signed, Modulo, Integer */ \
V(evmwhsmi, EVMWHSMI, 0x1000044D) \
/* Vector Multiply Word High Signed, Modulo, Integer to Accumulator */ \
V(evmwhsmia, EVMWHSMIA, 0x1000046D) \
/* Vector Multiply Word High Signed, Saturate, Fractional */ \
V(evmwhssf, EVMWHSSF, 0x10000447) \
/* Vector Multiply Word High Signed, Saturate, Fractional to Accumulator */ \
V(evmwhssfa, EVMWHSSFA, 0x10000467) \
/* Vector Multiply Word High Unsigned, Modulo, Integer */ \
V(evmwhumi, EVMWHUMI, 0x1000044C) \
/* Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator */ \
V(evmwhumia, EVMWHUMIA, 0x1000046C) \
/* Vector Multiply Word Low Signed, Modulo, Integer and Accumulate in */ \
/* Words */ \
V(evmwlsmiaaw, EVMWLSMIAAW, 0x10000549) \
/* Vector Multiply Word Low Signed, Modulo, Integer and Accumulate */ \
/* Negative in Words */ \
V(evmwlsmianw, EVMWLSMIANW, 0x100005C9) \
/* Vector Multiply Word Low Signed, Saturate, Integer and Accumulate in */ \
/* Words */ \
V(evmwlssiaaw, EVMWLSSIAAW, 0x10000541) \
/* Vector Multiply Word Low Signed, Saturate, Integer and Accumulate */ \
/* Negative in Words */ \
V(evmwlssianw, EVMWLSSIANW, 0x100005C1) \
/* Vector Multiply Word Low Unsigned, Modulo, Integer */ \
V(evmwlumi, EVMWLUMI, 0x10000448) \
/* Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator */ \
V(evmwlumia, EVMWLUMIA, 0x10000468) \
/* Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate in */ \
/* Words */ \
V(evmwlumiaaw, EVMWLUMIAAW, 0x10000548) \
/* Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate */ \
/* Negative in Words */ \
V(evmwlumianw, EVMWLUMIANW, 0x100005C8) \
/* Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate */ \
/* in Words */ \
V(evmwlusiaaw, EVMWLUSIAAW, 0x10000540) \
/* Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate */ \
/* Negative in Words */ \
V(evmwlusianw, EVMWLUSIANW, 0x100005C0) \
/* Vector Multiply Word Signed, Modulo, Fractional */ \
V(evmwsmf, EVMWSMF, 0x1000045B) \
/* Vector Multiply Word Signed, Modulo, Fractional to Accumulator */ \
V(evmwsmfa, EVMWSMFA, 0x1000047B) \
/* Vector Multiply Word Signed, Modulo, Fractional and Accumulate */ \
V(evmwsmfaa, EVMWSMFAA, 0x1000055B) \
/* Vector Multiply Word Signed, Modulo, Fractional and Accumulate */ \
/* Negative */ \
V(evmwsmfan, EVMWSMFAN, 0x100005DB) \
/* Vector Multiply Word Signed, Modulo, Integer */ \
V(evmwsmi, EVMWSMI, 0x10000459) \
/* Vector Multiply Word Signed, Modulo, Integer to Accumulator */ \
V(evmwsmia, EVMWSMIA, 0x10000479) \
/* Vector Multiply Word Signed, Modulo, Integer and Accumulate */ \
V(evmwsmiaa, EVMWSMIAA, 0x10000559) \
/* Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative */ \
V(evmwsmian, EVMWSMIAN, 0x100005D9) \
/* Vector Multiply Word Signed, Saturate, Fractional */ \
V(evmwssf, EVMWSSF, 0x10000453) \
/* Vector Multiply Word Signed, Saturate, Fractional to Accumulator */ \
V(evmwssfa, EVMWSSFA, 0x10000473) \
/* Vector Multiply Word Signed, Saturate, Fractional and Accumulate */ \
V(evmwssfaa, EVMWSSFAA, 0x10000553) \
/* Vector Multiply Word Signed, Saturate, Fractional and Accumulate */ \
/* Negative */ \
V(evmwssfan, EVMWSSFAN, 0x100005D3) \
/* Vector Multiply Word Unsigned, Modulo, Integer */ \
V(evmwumi, EVMWUMI, 0x10000458) \
/* Vector Multiply Word Unsigned, Modulo, Integer to Accumulator */ \
V(evmwumia, EVMWUMIA, 0x10000478) \
/* Vector Multiply Word Unsigned, Modulo, Integer and Accumulate */ \
V(evmwumiaa, EVMWUMIAA, 0x10000558) \
/* Vector Multiply Word Unsigned, Modulo, Integer and Accumulate */ \
/* Negative */ \
V(evmwumian, EVMWUMIAN, 0x100005D8) \
/* Vector NAND */ \
V(evnand, EVNAND, 0x1000021E) \
/* Vector Negate */ \
V(evneg, EVNEG, 0x10000209) \
/* Vector NOR */ \
V(evnor, EVNOR, 0x10000218) \
/* Vector OR */ \
V(evor, EVOR, 0x10000217) \
/* Vector OR with Complement */ \
V(evorc, EVORC, 0x1000021B) \
/* Vector Rotate Left Word */ \
V(evrlw, EVRLW, 0x10000228) \
/* Vector Rotate Left Word Immediate */ \
V(evrlwi, EVRLWI, 0x1000022A) \
/* Vector Round Word */ \
V(evrndw, EVRNDW, 0x1000020C) \
/* Vector Shift Left Word */ \
V(evslw, EVSLW, 0x10000224) \
/* Vector Shift Left Word Immediate */ \
V(evslwi, EVSLWI, 0x10000226) \
/* Vector Splat Fractional Immediate */ \
V(evsplatfi, EVSPLATFI, 0x1000022B) \
/* Vector Splat Immediate */ \
V(evsplati, EVSPLATI, 0x10000229) \
/* Vector Shift Right Word Immediate Signed */ \
V(evsrwis, EVSRWIS, 0x10000223) \
/* Vector Shift Right Word Immediate Unsigned */ \
V(evsrwiu, EVSRWIU, 0x10000222) \
/* Vector Shift Right Word Signed */ \
V(evsrws, EVSRWS, 0x10000221) \
/* Vector Shift Right Word Unsigned */ \
V(evsrwu, EVSRWU, 0x10000220) \
/* Vector Store Double of Double */ \
V(evstdd, EVSTDD, 0x10000321) \
/* Vector Store Double of Double Indexed */ \
V(evstddx, EVSTDDX, 0x10000320) \
/* Vector Store Double of Four Half Words */ \
V(evstdh, EVSTDH, 0x10000325) \
/* Vector Store Double of Four Half Words Indexed */ \
V(evstdhx, EVSTDHX, 0x10000324) \
/* Vector Store Double of Two Words */ \
V(evstdw, EVSTDW, 0x10000323) \
/* Vector Store Double of Two Words Indexed */ \
V(evstdwx, EVSTDWX, 0x10000322) \
/* Vector Store Word of Two Half Words from Even */ \
V(evstwhe, EVSTWHE, 0x10000331) \
/* Vector Store Word of Two Half Words from Even Indexed */ \
V(evstwhex, EVSTWHEX, 0x10000330) \
/* Vector Store Word of Two Half Words from Odd */ \
V(evstwho, EVSTWHO, 0x10000335) \
/* Vector Store Word of Two Half Words from Odd Indexed */ \
V(evstwhox, EVSTWHOX, 0x10000334) \
/* Vector Store Word of Word from Even */ \
V(evstwwe, EVSTWWE, 0x10000339) \
/* Vector Store Word of Word from Even Indexed */ \
V(evstwwex, EVSTWWEX, 0x10000338) \
/* Vector Store Word of Word from Odd */ \
V(evstwwo, EVSTWWO, 0x1000033D) \
/* Vector Store Word of Word from Odd Indexed */ \
V(evstwwox, EVSTWWOX, 0x1000033C) \
/* Vector Subtract Signed, Modulo, Integer to Accumulator Word */ \
V(evsubfsmiaaw, EVSUBFSMIAAW, 0x100004CB) \
/* Vector Subtract Signed, Saturate, Integer to Accumulator Word */ \
V(evsubfssiaaw, EVSUBFSSIAAW, 0x100004C3) \
/* Vector Subtract Unsigned, Modulo, Integer to Accumulator Word */ \
V(evsubfumiaaw, EVSUBFUMIAAW, 0x100004CA) \
/* Vector Subtract Unsigned, Saturate, Integer to Accumulator Word */ \
V(evsubfusiaaw, EVSUBFUSIAAW, 0x100004C2) \
/* Vector Subtract from Word */ \
V(evsubfw, EVSUBFW, 0x10000204) \
/* Vector Subtract Immediate from Word */ \
V(evsubifw, EVSUBIFW, 0x10000206) \
/* Vector XOR */ \
V(evxor, EVXOR, 0x10000216) \
/* Floating-Point Double-Precision Absolute Value */ \
V(efdabs, EFDABS, 0x100002E4) \
/* Floating-Point Double-Precision Add */ \
V(efdadd, EFDADD, 0x100002E0) \
/* Floating-Point Double-Precision Convert from Single-Precision */ \
V(efdcfs, EFDCFS, 0x100002EF) \
/* Convert Floating-Point Double-Precision from Signed Fraction */ \
V(efdcfsf, EFDCFSF, 0x100002F3) \
/* Convert Floating-Point Double-Precision from Signed Integer */ \
V(efdcfsi, EFDCFSI, 0x100002F1) \
/* Convert Floating-Point Double-Precision from Signed Integer */ \
/* Doubleword */ \
V(efdcfsid, EFDCFSID, 0x100002E3) \
/* Convert Floating-Point Double-Precision from Unsigned Fraction */ \
V(efdcfuf, EFDCFUF, 0x100002F2) \
/* Convert Floating-Point Double-Precision from Unsigned Integer */ \
V(efdcfui, EFDCFUI, 0x100002F0) \
/* Convert Floating-Point Double-Precision fromUnsigned Integer */ \
/* Doubleword */ \
V(efdcfuid, EFDCFUID, 0x100002E2) \
/* Floating-Point Double-Precision Compare Equal */ \
V(efdcmpeq, EFDCMPEQ, 0x100002EE) \
/* Floating-Point Double-Precision Compare Greater Than */ \
V(efdcmpgt, EFDCMPGT, 0x100002EC) \
/* Floating-Point Double-Precision Compare Less Than */ \
V(efdcmplt, EFDCMPLT, 0x100002ED) \
/* Convert Floating-Point Double-Precision to Signed Fraction */ \
V(efdctsf, EFDCTSF, 0x100002F7) \
/* Convert Floating-Point Double-Precision to Signed Integer */ \
V(efdctsi, EFDCTSI, 0x100002F5) \
/* Convert Floating-Point Double-Precision to Signed Integer Doubleword */ \
/* with Round toward Zero */ \
V(efdctsidz, EFDCTSIDZ, 0x100002EB) \
/* Convert Floating-Point Double-Precision to Signed Integer with Round */ \
/* toward Zero */ \
V(efdctsiz, EFDCTSIZ, 0x100002FA) \
/* Convert Floating-Point Double-Precision to Unsigned Fraction */ \
V(efdctuf, EFDCTUF, 0x100002F6) \
/* Convert Floating-Point Double-Precision to Unsigned Integer */ \
V(efdctui, EFDCTUI, 0x100002F4) \
/* Convert Floating-Point Double-Precision to Unsigned Integer */ \
/* Doubleword with Round toward Zero */ \
V(efdctuidz, EFDCTUIDZ, 0x100002EA) \
/* Convert Floating-Point Double-Precision to Unsigned Integer with */ \
/* Round toward Zero */ \
V(efdctuiz, EFDCTUIZ, 0x100002F8) \
/* Floating-Point Double-Precision Divide */ \
V(efddiv, EFDDIV, 0x100002E9) \
/* Floating-Point Double-Precision Multiply */ \
V(efdmul, EFDMUL, 0x100002E8) \
/* Floating-Point Double-Precision Negative Absolute Value */ \
V(efdnabs, EFDNABS, 0x100002E5) \
/* Floating-Point Double-Precision Negate */ \
V(efdneg, EFDNEG, 0x100002E6) \
/* Floating-Point Double-Precision Subtract */ \
V(efdsub, EFDSUB, 0x100002E1) \
/* Floating-Point Double-Precision Test Equal */ \
V(efdtsteq, EFDTSTEQ, 0x100002FE) \
/* Floating-Point Double-Precision Test Greater Than */ \
V(efdtstgt, EFDTSTGT, 0x100002FC) \
/* Floating-Point Double-Precision Test Less Than */ \
V(efdtstlt, EFDTSTLT, 0x100002FD) \
/* Floating-Point Single-Precision Convert from Double-Precision */ \
V(efscfd, EFSCFD, 0x100002CF) \
/* Floating-Point Absolute Value */ \
V(efsabs, EFSABS, 0x100002C4) \
/* Floating-Point Add */ \
V(efsadd, EFSADD, 0x100002C0) \
/* Convert Floating-Point from Signed Fraction */ \
V(efscfsf, EFSCFSF, 0x100002D3) \
/* Convert Floating-Point from Signed Integer */ \
V(efscfsi, EFSCFSI, 0x100002D1) \