/
assembler-mips64.h
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assembler-mips64.h
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// Copyright (c) 1994-2006 Sun Microsystems Inc.
// All Rights Reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistribution in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of Sun Microsystems or the names of contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// The original source code covered by the above license above has been
// modified significantly by Google Inc.
// Copyright 2012 the V8 project authors. All rights reserved.
#ifndef V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_
#define V8_CODEGEN_MIPS64_ASSEMBLER_MIPS64_H_
#include <stdio.h>
#include <memory>
#include <set>
#include "src/codegen/assembler.h"
#include "src/codegen/external-reference.h"
#include "src/codegen/label.h"
#include "src/codegen/machine-type.h"
#include "src/codegen/mips64/constants-mips64.h"
#include "src/codegen/mips64/register-mips64.h"
#include "src/objects/contexts.h"
#include "src/objects/smi.h"
namespace v8 {
namespace internal {
class SafepointTableBuilder;
// -----------------------------------------------------------------------------
// Machine instruction Operands.
constexpr int kSmiShift = kSmiTagSize + kSmiShiftSize;
constexpr uint64_t kSmiShiftMask = (1UL << kSmiShift) - 1;
// Class Operand represents a shifter operand in data processing instructions.
class Operand {
public:
// Immediate.
V8_INLINE explicit Operand(int64_t immediate,
RelocInfo::Mode rmode = RelocInfo::NONE)
: rm_(no_reg), rmode_(rmode) {
value_.immediate = immediate;
}
V8_INLINE explicit Operand(const ExternalReference& f)
: rm_(no_reg), rmode_(RelocInfo::EXTERNAL_REFERENCE) {
value_.immediate = static_cast<int64_t>(f.address());
}
explicit Operand(Handle<HeapObject> handle);
V8_INLINE explicit Operand(Smi value) : rm_(no_reg), rmode_(RelocInfo::NONE) {
value_.immediate = static_cast<intptr_t>(value.ptr());
}
static Operand EmbeddedNumber(double number); // Smi or HeapNumber.
static Operand EmbeddedStringConstant(const StringConstantBase* str);
// Register.
V8_INLINE explicit Operand(Register rm) : rm_(rm) {}
// Return true if this is a register operand.
V8_INLINE bool is_reg() const;
inline int64_t immediate() const;
bool IsImmediate() const { return !rm_.is_valid(); }
HeapObjectRequest heap_object_request() const {
DCHECK(IsHeapObjectRequest());
return value_.heap_object_request;
}
bool IsHeapObjectRequest() const {
DCHECK_IMPLIES(is_heap_object_request_, IsImmediate());
DCHECK_IMPLIES(is_heap_object_request_,
rmode_ == RelocInfo::FULL_EMBEDDED_OBJECT ||
rmode_ == RelocInfo::CODE_TARGET);
return is_heap_object_request_;
}
Register rm() const { return rm_; }
RelocInfo::Mode rmode() const { return rmode_; }
private:
Register rm_;
union Value {
Value() {}
HeapObjectRequest heap_object_request; // if is_heap_object_request_
int64_t immediate; // otherwise
} value_; // valid if rm_ == no_reg
bool is_heap_object_request_ = false;
RelocInfo::Mode rmode_;
friend class Assembler;
friend class MacroAssembler;
};
// On MIPS we have only one addressing mode with base_reg + offset.
// Class MemOperand represents a memory operand in load and store instructions.
class V8_EXPORT_PRIVATE MemOperand : public Operand {
public:
// Immediate value attached to offset.
enum OffsetAddend { offset_minus_one = -1, offset_zero = 0 };
explicit MemOperand(Register rn, int32_t offset = 0);
explicit MemOperand(Register rn, int32_t unit, int32_t multiplier,
OffsetAddend offset_addend = offset_zero);
int32_t offset() const { return offset_; }
bool OffsetIsInt16Encodable() const { return is_int16(offset_); }
private:
int32_t offset_;
friend class Assembler;
};
class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
public:
// Create an assembler. Instructions and relocation information are emitted
// into a buffer, with the instructions starting from the beginning and the
// relocation information starting from the end of the buffer. See CodeDesc
// for a detailed comment on the layout (globals.h).
//
// If the provided buffer is nullptr, the assembler allocates and grows its
// own buffer. Otherwise it takes ownership of the provided buffer.
explicit Assembler(const AssemblerOptions&,
std::unique_ptr<AssemblerBuffer> = {});
virtual ~Assembler() {}
// GetCode emits any pending (non-emitted) code and fills the descriptor desc.
static constexpr int kNoHandlerTable = 0;
static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr;
void GetCode(Isolate* isolate, CodeDesc* desc,
SafepointTableBuilder* safepoint_table_builder,
int handler_table_offset);
// Convenience wrapper for code without safepoint or handler tables.
void GetCode(Isolate* isolate, CodeDesc* desc) {
GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable);
}
// This function is called when on-heap-compilation invariants are
// invalidated. For instance, when the assembler buffer grows or a GC happens
// between Code object allocation and Code object finalization.
void FixOnHeapReferences(bool update_embedded_objects = true);
// This function is called when we fallback from on-heap to off-heap
// compilation and patch on-heap references to handles.
void FixOnHeapReferencesToHandles();
// Unused on this architecture.
void MaybeEmitOutOfLineConstantPool() {}
// Mips uses BlockTrampolinePool to prevent generating trampoline inside a
// continuous instruction block. For Call instruction, it prevents generating
// trampoline between jalr and delay slot instruction. In the destructor of
// BlockTrampolinePool, it must check if it needs to generate trampoline
// immediately, if it does not do this, the branch range will go beyond the
// max branch offset, that means the pc_offset after call CheckTrampolinePool
// may be not the Call instruction's location. So we use last_call_pc here for
// safepoint record.
int pc_offset_for_safepoint() {
#ifdef DEBUG
Instr instr1 =
instr_at(static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize));
Instr instr2 = instr_at(
static_cast<int>(last_call_pc_ - buffer_start_ - kInstrSize * 2));
if (GetOpcodeField(instr1) != SPECIAL) { // instr1 == jialc.
DCHECK((kArchVariant == kMips64r6) && GetOpcodeField(instr1) == POP76 &&
GetRs(instr1) == 0);
} else {
if (GetFunctionField(instr1) == SLL) { // instr1 == nop, instr2 == jalr.
DCHECK(GetOpcodeField(instr2) == SPECIAL &&
GetFunctionField(instr2) == JALR);
} else { // instr1 == jalr.
DCHECK(GetFunctionField(instr1) == JALR);
}
}
#endif
return static_cast<int>(last_call_pc_ - buffer_start_);
}
// Label operations & relative jumps (PPUM Appendix D).
//
// Takes a branch opcode (cc) and a label (L) and generates
// either a backward branch or a forward branch and links it
// to the label fixup chain. Usage:
//
// Label L; // unbound label
// j(cc, &L); // forward branch to unbound label
// bind(&L); // bind label to the current pc
// j(cc, &L); // backward branch to bound label
// bind(&L); // illegal: a label may be bound only once
//
// Note: The same Label can be used for forward and backward branches
// but it may be bound only once.
void bind(Label* L); // Binds an unbound label L to current code position.
enum OffsetSize : int { kOffset26 = 26, kOffset21 = 21, kOffset16 = 16 };
// Determines if Label is bound and near enough so that branch instruction
// can be used to reach it, instead of jump instruction.
bool is_near(Label* L);
bool is_near(Label* L, OffsetSize bits);
bool is_near_branch(Label* L);
inline bool is_near_pre_r6(Label* L) {
DCHECK(!(kArchVariant == kMips64r6));
return pc_offset() - L->pos() < kMaxBranchOffset - 4 * kInstrSize;
}
inline bool is_near_r6(Label* L) {
DCHECK_EQ(kArchVariant, kMips64r6);
return pc_offset() - L->pos() < kMaxCompactBranchOffset - 4 * kInstrSize;
}
int BranchOffset(Instr instr);
// Returns the branch offset to the given label from the current code
// position. Links the label to the current position if it is still unbound.
// Manages the jump elimination optimization if the second parameter is true.
int32_t branch_offset_helper(Label* L, OffsetSize bits);
inline int32_t branch_offset(Label* L) {
return branch_offset_helper(L, OffsetSize::kOffset16);
}
inline int32_t branch_offset21(Label* L) {
return branch_offset_helper(L, OffsetSize::kOffset21);
}
inline int32_t branch_offset26(Label* L) {
return branch_offset_helper(L, OffsetSize::kOffset26);
}
inline int32_t shifted_branch_offset(Label* L) {
return branch_offset(L) >> 2;
}
inline int32_t shifted_branch_offset21(Label* L) {
return branch_offset21(L) >> 2;
}
inline int32_t shifted_branch_offset26(Label* L) {
return branch_offset26(L) >> 2;
}
uint64_t jump_address(Label* L);
uint64_t jump_offset(Label* L);
uint64_t branch_long_offset(Label* L);
// Puts a labels target address at the given position.
// The high 8 bits are set to zero.
void label_at_put(Label* L, int at_offset);
// Read/Modify the code target address in the branch/call instruction at pc.
// The isolate argument is unused (and may be nullptr) when skipping flushing.
static Address target_address_at(Address pc);
V8_INLINE static void set_target_address_at(
Address pc, Address target,
ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) {
set_target_value_at(pc, target, icache_flush_mode);
}
// On MIPS there is no Constant Pool so we skip that parameter.
V8_INLINE static Address target_address_at(Address pc,
Address constant_pool) {
return target_address_at(pc);
}
V8_INLINE static void set_target_address_at(
Address pc, Address constant_pool, Address target,
ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) {
set_target_address_at(pc, target, icache_flush_mode);
}
static void set_target_value_at(
Address pc, uint64_t target,
ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED);
static void JumpLabelToJumpRegister(Address pc);
// This sets the branch destination (which gets loaded at the call address).
// This is for calls and branches within generated code. The serializer
// has already deserialized the lui/ori instructions etc.
inline static void deserialization_set_special_target_at(
Address instruction_payload, Code code, Address target);
// Get the size of the special target encoded at 'instruction_payload'.
inline static int deserialization_special_target_size(
Address instruction_payload);
// This sets the internal reference at the pc.
inline static void deserialization_set_target_internal_reference_at(
Address pc, Address target,
RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE);
// Difference between address of current opcode and target address offset.
static constexpr int kBranchPCOffset = kInstrSize;
// Difference between address of current opcode and target address offset,
// when we are generatinga sequence of instructions for long relative PC
// branches
static constexpr int kLongBranchPCOffset = 3 * kInstrSize;
// Adjust ra register in branch delay slot of bal instruction so to skip
// instructions not needed after optimization of PIC in
// TurboAssembler::BranchAndLink method.
static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 4 * kInstrSize;
// Here we are patching the address in the LUI/ORI instruction pair.
// These values are used in the serialization process and must be zero for
// MIPS platform, as Code, Embedded Object or External-reference pointers
// are split across two consecutive instructions and don't exist separately
// in the code, so the serializer should not step forwards in memory after
// a target is resolved and written.
static constexpr int kSpecialTargetSize = 0;
// Number of consecutive instructions used to store 32bit/64bit constant.
// This constant was used in RelocInfo::target_address_address() function
// to tell serializer address of the instruction that follows
// LUI/ORI instruction pair.
static constexpr int kInstructionsFor32BitConstant = 2;
static constexpr int kInstructionsFor64BitConstant = 4;
// Difference between address of current opcode and value read from pc
// register.
static constexpr int kPcLoadDelta = 4;
// Max offset for instructions with 16-bit offset field
static constexpr int kMaxBranchOffset = (1 << (18 - 1)) - 1;
// Max offset for compact branch instructions with 26-bit offset field
static constexpr int kMaxCompactBranchOffset = (1 << (28 - 1)) - 1;
static constexpr int kTrampolineSlotsSize =
kArchVariant == kMips64r6 ? 2 * kInstrSize : 7 * kInstrSize;
RegList* GetScratchRegisterList() { return &scratch_register_list_; }
// ---------------------------------------------------------------------------
// Code generation.
// Insert the smallest number of nop instructions
// possible to align the pc offset to a multiple
// of m. m must be a power of 2 (>= 4).
void Align(int m);
// Insert the smallest number of zero bytes possible to align the pc offset
// to a mulitple of m. m must be a power of 2 (>= 2).
void DataAlign(int m);
// Aligns code to something that's optimal for a jump target for the platform.
void CodeTargetAlign();
void LoopHeaderAlign() { CodeTargetAlign(); }
// Different nop operations are used by the code generator to detect certain
// states of the generated code.
enum NopMarkerTypes {
NON_MARKING_NOP = 0,
DEBUG_BREAK_NOP,
// IC markers.
PROPERTY_ACCESS_INLINED,
PROPERTY_ACCESS_INLINED_CONTEXT,
PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
// Helper values.
LAST_CODE_MARKER,
FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED,
};
// Type == 0 is the default non-marking nop. For mips this is a
// sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero
// marking, to avoid conflict with ssnop and ehb instructions.
void nop(unsigned int type = 0) {
DCHECK_LT(type, 32);
Register nop_rt_reg = (type == 0) ? zero_reg : at;
sll(zero_reg, nop_rt_reg, type, true);
}
// --------Branch-and-jump-instructions----------
// We don't use likely variant of instructions.
void b(int16_t offset);
inline void b(Label* L) { b(shifted_branch_offset(L)); }
void bal(int16_t offset);
inline void bal(Label* L) { bal(shifted_branch_offset(L)); }
void bc(int32_t offset);
inline void bc(Label* L) { bc(shifted_branch_offset26(L)); }
void balc(int32_t offset);
inline void balc(Label* L) { balc(shifted_branch_offset26(L)); }
void beq(Register rs, Register rt, int16_t offset);
inline void beq(Register rs, Register rt, Label* L) {
beq(rs, rt, shifted_branch_offset(L));
}
void bgez(Register rs, int16_t offset);
void bgezc(Register rt, int16_t offset);
inline void bgezc(Register rt, Label* L) {
bgezc(rt, shifted_branch_offset(L));
}
void bgeuc(Register rs, Register rt, int16_t offset);
inline void bgeuc(Register rs, Register rt, Label* L) {
bgeuc(rs, rt, shifted_branch_offset(L));
}
void bgec(Register rs, Register rt, int16_t offset);
inline void bgec(Register rs, Register rt, Label* L) {
bgec(rs, rt, shifted_branch_offset(L));
}
void bgezal(Register rs, int16_t offset);
void bgezalc(Register rt, int16_t offset);
inline void bgezalc(Register rt, Label* L) {
bgezalc(rt, shifted_branch_offset(L));
}
void bgezall(Register rs, int16_t offset);
inline void bgezall(Register rs, Label* L) {
bgezall(rs, branch_offset(L) >> 2);
}
void bgtz(Register rs, int16_t offset);
void bgtzc(Register rt, int16_t offset);
inline void bgtzc(Register rt, Label* L) {
bgtzc(rt, shifted_branch_offset(L));
}
void blez(Register rs, int16_t offset);
void blezc(Register rt, int16_t offset);
inline void blezc(Register rt, Label* L) {
blezc(rt, shifted_branch_offset(L));
}
void bltz(Register rs, int16_t offset);
void bltzc(Register rt, int16_t offset);
inline void bltzc(Register rt, Label* L) {
bltzc(rt, shifted_branch_offset(L));
}
void bltuc(Register rs, Register rt, int16_t offset);
inline void bltuc(Register rs, Register rt, Label* L) {
bltuc(rs, rt, shifted_branch_offset(L));
}
void bltc(Register rs, Register rt, int16_t offset);
inline void bltc(Register rs, Register rt, Label* L) {
bltc(rs, rt, shifted_branch_offset(L));
}
void bltzal(Register rs, int16_t offset);
void nal() { bltzal(zero_reg, 0); }
void blezalc(Register rt, int16_t offset);
inline void blezalc(Register rt, Label* L) {
blezalc(rt, shifted_branch_offset(L));
}
void bltzalc(Register rt, int16_t offset);
inline void bltzalc(Register rt, Label* L) {
bltzalc(rt, shifted_branch_offset(L));
}
void bgtzalc(Register rt, int16_t offset);
inline void bgtzalc(Register rt, Label* L) {
bgtzalc(rt, shifted_branch_offset(L));
}
void beqzalc(Register rt, int16_t offset);
inline void beqzalc(Register rt, Label* L) {
beqzalc(rt, shifted_branch_offset(L));
}
void beqc(Register rs, Register rt, int16_t offset);
inline void beqc(Register rs, Register rt, Label* L) {
beqc(rs, rt, shifted_branch_offset(L));
}
void beqzc(Register rs, int32_t offset);
inline void beqzc(Register rs, Label* L) {
beqzc(rs, shifted_branch_offset21(L));
}
void bnezalc(Register rt, int16_t offset);
inline void bnezalc(Register rt, Label* L) {
bnezalc(rt, shifted_branch_offset(L));
}
void bnec(Register rs, Register rt, int16_t offset);
inline void bnec(Register rs, Register rt, Label* L) {
bnec(rs, rt, shifted_branch_offset(L));
}
void bnezc(Register rt, int32_t offset);
inline void bnezc(Register rt, Label* L) {
bnezc(rt, shifted_branch_offset21(L));
}
void bne(Register rs, Register rt, int16_t offset);
inline void bne(Register rs, Register rt, Label* L) {
bne(rs, rt, shifted_branch_offset(L));
}
void bovc(Register rs, Register rt, int16_t offset);
inline void bovc(Register rs, Register rt, Label* L) {
bovc(rs, rt, shifted_branch_offset(L));
}
void bnvc(Register rs, Register rt, int16_t offset);
inline void bnvc(Register rs, Register rt, Label* L) {
bnvc(rs, rt, shifted_branch_offset(L));
}
// Never use the int16_t b(l)cond version with a branch offset
// instead of using the Label* version.
void jalr(Register rs, Register rd = ra);
void jr(Register target);
void jic(Register rt, int16_t offset);
void jialc(Register rt, int16_t offset);
// Following instructions are deprecated and require 256 MB
// code alignment. Use PC-relative instructions instead.
void j(int64_t target);
void jal(int64_t target);
void j(Label* target);
void jal(Label* target);
// -------Data-processing-instructions---------
// Arithmetic.
void addu(Register rd, Register rs, Register rt);
void subu(Register rd, Register rs, Register rt);
void div(Register rs, Register rt);
void divu(Register rs, Register rt);
void ddiv(Register rs, Register rt);
void ddivu(Register rs, Register rt);
void div(Register rd, Register rs, Register rt);
void divu(Register rd, Register rs, Register rt);
void ddiv(Register rd, Register rs, Register rt);
void ddivu(Register rd, Register rs, Register rt);
void mod(Register rd, Register rs, Register rt);
void modu(Register rd, Register rs, Register rt);
void dmod(Register rd, Register rs, Register rt);
void dmodu(Register rd, Register rs, Register rt);
void mul(Register rd, Register rs, Register rt);
void muh(Register rd, Register rs, Register rt);
void mulu(Register rd, Register rs, Register rt);
void muhu(Register rd, Register rs, Register rt);
void mult(Register rs, Register rt);
void multu(Register rs, Register rt);
void dmul(Register rd, Register rs, Register rt);
void dmuh(Register rd, Register rs, Register rt);
void dmulu(Register rd, Register rs, Register rt);
void dmuhu(Register rd, Register rs, Register rt);
void daddu(Register rd, Register rs, Register rt);
void dsubu(Register rd, Register rs, Register rt);
void dmult(Register rs, Register rt);
void dmultu(Register rs, Register rt);
void addiu(Register rd, Register rs, int32_t j);
void daddiu(Register rd, Register rs, int32_t j);
// Logical.
void and_(Register rd, Register rs, Register rt);
void or_(Register rd, Register rs, Register rt);
void xor_(Register rd, Register rs, Register rt);
void nor(Register rd, Register rs, Register rt);
void andi(Register rd, Register rs, int32_t j);
void ori(Register rd, Register rs, int32_t j);
void xori(Register rd, Register rs, int32_t j);
void lui(Register rd, int32_t j);
void aui(Register rt, Register rs, int32_t j);
void daui(Register rt, Register rs, int32_t j);
void dahi(Register rs, int32_t j);
void dati(Register rs, int32_t j);
// Shifts.
// Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
// and may cause problems in normal code. coming_from_nop makes sure this
// doesn't happen.
void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
void sllv(Register rd, Register rt, Register rs);
void srl(Register rd, Register rt, uint16_t sa);
void srlv(Register rd, Register rt, Register rs);
void sra(Register rt, Register rd, uint16_t sa);
void srav(Register rt, Register rd, Register rs);
void rotr(Register rd, Register rt, uint16_t sa);
void rotrv(Register rd, Register rt, Register rs);
void dsll(Register rd, Register rt, uint16_t sa);
void dsllv(Register rd, Register rt, Register rs);
void dsrl(Register rd, Register rt, uint16_t sa);
void dsrlv(Register rd, Register rt, Register rs);
void drotr(Register rd, Register rt, uint16_t sa);
void drotr32(Register rd, Register rt, uint16_t sa);
void drotrv(Register rd, Register rt, Register rs);
void dsra(Register rt, Register rd, uint16_t sa);
void dsrav(Register rd, Register rt, Register rs);
void dsll32(Register rt, Register rd, uint16_t sa);
void dsrl32(Register rt, Register rd, uint16_t sa);
void dsra32(Register rt, Register rd, uint16_t sa);
// ------------Memory-instructions-------------
void lb(Register rd, const MemOperand& rs);
void lbu(Register rd, const MemOperand& rs);
void lh(Register rd, const MemOperand& rs);
void lhu(Register rd, const MemOperand& rs);
void lw(Register rd, const MemOperand& rs);
void lwu(Register rd, const MemOperand& rs);
void lwl(Register rd, const MemOperand& rs);
void lwr(Register rd, const MemOperand& rs);
void sb(Register rd, const MemOperand& rs);
void sh(Register rd, const MemOperand& rs);
void sw(Register rd, const MemOperand& rs);
void swl(Register rd, const MemOperand& rs);
void swr(Register rd, const MemOperand& rs);
void ldl(Register rd, const MemOperand& rs);
void ldr(Register rd, const MemOperand& rs);
void sdl(Register rd, const MemOperand& rs);
void sdr(Register rd, const MemOperand& rs);
void ld(Register rd, const MemOperand& rs);
void sd(Register rd, const MemOperand& rs);
// ----------Atomic instructions--------------
void ll(Register rd, const MemOperand& rs);
void sc(Register rd, const MemOperand& rs);
void lld(Register rd, const MemOperand& rs);
void scd(Register rd, const MemOperand& rs);
// ---------PC-Relative-instructions-----------
void addiupc(Register rs, int32_t imm19);
void lwpc(Register rs, int32_t offset19);
void lwupc(Register rs, int32_t offset19);
void ldpc(Register rs, int32_t offset18);
void auipc(Register rs, int16_t imm16);
void aluipc(Register rs, int16_t imm16);
// ----------------Prefetch--------------------
void pref(int32_t hint, const MemOperand& rs);
// -------------Misc-instructions--------------
// Break / Trap instructions.
void break_(uint32_t code, bool break_as_stop = false);
void stop(uint32_t code = kMaxStopCode);
void tge(Register rs, Register rt, uint16_t code);
void tgeu(Register rs, Register rt, uint16_t code);
void tlt(Register rs, Register rt, uint16_t code);
void tltu(Register rs, Register rt, uint16_t code);
void teq(Register rs, Register rt, uint16_t code);
void tne(Register rs, Register rt, uint16_t code);
// Memory barrier instruction.
void sync();
// Move from HI/LO register.
void mfhi(Register rd);
void mflo(Register rd);
// Set on less than.
void slt(Register rd, Register rs, Register rt);
void sltu(Register rd, Register rs, Register rt);
void slti(Register rd, Register rs, int32_t j);
void sltiu(Register rd, Register rs, int32_t j);
// Conditional move.
void movz(Register rd, Register rs, Register rt);
void movn(Register rd, Register rs, Register rt);
void movt(Register rd, Register rs, uint16_t cc = 0);
void movf(Register rd, Register rs, uint16_t cc = 0);
void sel(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
void sel_s(FPURegister fd, FPURegister fs, FPURegister ft);
void sel_d(FPURegister fd, FPURegister fs, FPURegister ft);
void seleqz(Register rd, Register rs, Register rt);
void seleqz(SecondaryField fmt, FPURegister fd, FPURegister fs,
FPURegister ft);
void selnez(Register rs, Register rt, Register rd);
void selnez(SecondaryField fmt, FPURegister fd, FPURegister fs,
FPURegister ft);
void seleqz_d(FPURegister fd, FPURegister fs, FPURegister ft);
void seleqz_s(FPURegister fd, FPURegister fs, FPURegister ft);
void selnez_d(FPURegister fd, FPURegister fs, FPURegister ft);
void selnez_s(FPURegister fd, FPURegister fs, FPURegister ft);
void movz_s(FPURegister fd, FPURegister fs, Register rt);
void movz_d(FPURegister fd, FPURegister fs, Register rt);
void movt_s(FPURegister fd, FPURegister fs, uint16_t cc = 0);
void movt_d(FPURegister fd, FPURegister fs, uint16_t cc = 0);
void movf_s(FPURegister fd, FPURegister fs, uint16_t cc = 0);
void movf_d(FPURegister fd, FPURegister fs, uint16_t cc = 0);
void movn_s(FPURegister fd, FPURegister fs, Register rt);
void movn_d(FPURegister fd, FPURegister fs, Register rt);
// Bit twiddling.
void clz(Register rd, Register rs);
void dclz(Register rd, Register rs);
void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
void dext_(Register rt, Register rs, uint16_t pos, uint16_t size);
void dextm_(Register rt, Register rs, uint16_t pos, uint16_t size);
void dextu_(Register rt, Register rs, uint16_t pos, uint16_t size);
void dins_(Register rt, Register rs, uint16_t pos, uint16_t size);
void dinsm_(Register rt, Register rs, uint16_t pos, uint16_t size);
void dinsu_(Register rt, Register rs, uint16_t pos, uint16_t size);
void bitswap(Register rd, Register rt);
void dbitswap(Register rd, Register rt);
void align(Register rd, Register rs, Register rt, uint8_t bp);
void dalign(Register rd, Register rs, Register rt, uint8_t bp);
void wsbh(Register rd, Register rt);
void dsbh(Register rd, Register rt);
void dshd(Register rd, Register rt);
void seh(Register rd, Register rt);
void seb(Register rd, Register rt);
// --------Coprocessor-instructions----------------
// Load, store, and move.
void lwc1(FPURegister fd, const MemOperand& src);
void ldc1(FPURegister fd, const MemOperand& src);
void swc1(FPURegister fs, const MemOperand& dst);
void sdc1(FPURegister fs, const MemOperand& dst);
void mtc1(Register rt, FPURegister fs);
void mthc1(Register rt, FPURegister fs);
void dmtc1(Register rt, FPURegister fs);
void mfc1(Register rt, FPURegister fs);
void mfhc1(Register rt, FPURegister fs);
void dmfc1(Register rt, FPURegister fs);
void ctc1(Register rt, FPUControlRegister fs);
void cfc1(Register rt, FPUControlRegister fs);
// Arithmetic.
void add_s(FPURegister fd, FPURegister fs, FPURegister ft);
void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
void sub_s(FPURegister fd, FPURegister fs, FPURegister ft);
void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
void mul_s(FPURegister fd, FPURegister fs, FPURegister ft);
void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
void madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
void msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
void msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
void maddf_s(FPURegister fd, FPURegister fs, FPURegister ft);
void maddf_d(FPURegister fd, FPURegister fs, FPURegister ft);
void msubf_s(FPURegister fd, FPURegister fs, FPURegister ft);
void msubf_d(FPURegister fd, FPURegister fs, FPURegister ft);
void div_s(FPURegister fd, FPURegister fs, FPURegister ft);
void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
void abs_s(FPURegister fd, FPURegister fs);
void abs_d(FPURegister fd, FPURegister fs);
void mov_d(FPURegister fd, FPURegister fs);
void mov_s(FPURegister fd, FPURegister fs);
void neg_s(FPURegister fd, FPURegister fs);
void neg_d(FPURegister fd, FPURegister fs);
void sqrt_s(FPURegister fd, FPURegister fs);
void sqrt_d(FPURegister fd, FPURegister fs);
void rsqrt_s(FPURegister fd, FPURegister fs);
void rsqrt_d(FPURegister fd, FPURegister fs);
void recip_d(FPURegister fd, FPURegister fs);
void recip_s(FPURegister fd, FPURegister fs);
// Conversion.
void cvt_w_s(FPURegister fd, FPURegister fs);
void cvt_w_d(FPURegister fd, FPURegister fs);
void trunc_w_s(FPURegister fd, FPURegister fs);
void trunc_w_d(FPURegister fd, FPURegister fs);
void round_w_s(FPURegister fd, FPURegister fs);
void round_w_d(FPURegister fd, FPURegister fs);
void floor_w_s(FPURegister fd, FPURegister fs);
void floor_w_d(FPURegister fd, FPURegister fs);
void ceil_w_s(FPURegister fd, FPURegister fs);
void ceil_w_d(FPURegister fd, FPURegister fs);
void rint_s(FPURegister fd, FPURegister fs);
void rint_d(FPURegister fd, FPURegister fs);
void rint(SecondaryField fmt, FPURegister fd, FPURegister fs);
void cvt_l_s(FPURegister fd, FPURegister fs);
void cvt_l_d(FPURegister fd, FPURegister fs);
void trunc_l_s(FPURegister fd, FPURegister fs);
void trunc_l_d(FPURegister fd, FPURegister fs);
void round_l_s(FPURegister fd, FPURegister fs);
void round_l_d(FPURegister fd, FPURegister fs);
void floor_l_s(FPURegister fd, FPURegister fs);
void floor_l_d(FPURegister fd, FPURegister fs);
void ceil_l_s(FPURegister fd, FPURegister fs);
void ceil_l_d(FPURegister fd, FPURegister fs);
void class_s(FPURegister fd, FPURegister fs);
void class_d(FPURegister fd, FPURegister fs);
void min(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
void mina(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
void max(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
void maxa(SecondaryField fmt, FPURegister fd, FPURegister fs, FPURegister ft);
void min_s(FPURegister fd, FPURegister fs, FPURegister ft);
void min_d(FPURegister fd, FPURegister fs, FPURegister ft);
void max_s(FPURegister fd, FPURegister fs, FPURegister ft);
void max_d(FPURegister fd, FPURegister fs, FPURegister ft);
void mina_s(FPURegister fd, FPURegister fs, FPURegister ft);
void mina_d(FPURegister fd, FPURegister fs, FPURegister ft);
void maxa_s(FPURegister fd, FPURegister fs, FPURegister ft);
void maxa_d(FPURegister fd, FPURegister fs, FPURegister ft);
void cvt_s_w(FPURegister fd, FPURegister fs);
void cvt_s_l(FPURegister fd, FPURegister fs);
void cvt_s_d(FPURegister fd, FPURegister fs);
void cvt_d_w(FPURegister fd, FPURegister fs);
void cvt_d_l(FPURegister fd, FPURegister fs);
void cvt_d_s(FPURegister fd, FPURegister fs);
// Conditions and branches for MIPSr6.
void cmp(FPUCondition cond, SecondaryField fmt, FPURegister fd,
FPURegister ft, FPURegister fs);
void cmp_s(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft);
void cmp_d(FPUCondition cond, FPURegister fd, FPURegister fs, FPURegister ft);
void bc1eqz(int16_t offset, FPURegister ft);
inline void bc1eqz(Label* L, FPURegister ft) {
bc1eqz(shifted_branch_offset(L), ft);
}
void bc1nez(int16_t offset, FPURegister ft);
inline void bc1nez(Label* L, FPURegister ft) {
bc1nez(shifted_branch_offset(L), ft);
}
// Conditions and branches for non MIPSr6.
void c(FPUCondition cond, SecondaryField fmt, FPURegister ft, FPURegister fs,
uint16_t cc = 0);
void c_s(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0);
void c_d(FPUCondition cond, FPURegister ft, FPURegister fs, uint16_t cc = 0);
void bc1f(int16_t offset, uint16_t cc = 0);
inline void bc1f(Label* L, uint16_t cc = 0) {
bc1f(shifted_branch_offset(L), cc);
}
void bc1t(int16_t offset, uint16_t cc = 0);
inline void bc1t(Label* L, uint16_t cc = 0) {
bc1t(shifted_branch_offset(L), cc);
}
void fcmp(FPURegister src1, const double src2, FPUCondition cond);
// MSA instructions
void bz_v(MSARegister wt, int16_t offset);
inline void bz_v(MSARegister wt, Label* L) {
bz_v(wt, shifted_branch_offset(L));
}
void bz_b(MSARegister wt, int16_t offset);
inline void bz_b(MSARegister wt, Label* L) {
bz_b(wt, shifted_branch_offset(L));
}
void bz_h(MSARegister wt, int16_t offset);
inline void bz_h(MSARegister wt, Label* L) {
bz_h(wt, shifted_branch_offset(L));
}
void bz_w(MSARegister wt, int16_t offset);
inline void bz_w(MSARegister wt, Label* L) {
bz_w(wt, shifted_branch_offset(L));
}
void bz_d(MSARegister wt, int16_t offset);
inline void bz_d(MSARegister wt, Label* L) {
bz_d(wt, shifted_branch_offset(L));
}
void bnz_v(MSARegister wt, int16_t offset);
inline void bnz_v(MSARegister wt, Label* L) {
bnz_v(wt, shifted_branch_offset(L));
}
void bnz_b(MSARegister wt, int16_t offset);
inline void bnz_b(MSARegister wt, Label* L) {
bnz_b(wt, shifted_branch_offset(L));
}
void bnz_h(MSARegister wt, int16_t offset);
inline void bnz_h(MSARegister wt, Label* L) {
bnz_h(wt, shifted_branch_offset(L));
}
void bnz_w(MSARegister wt, int16_t offset);
inline void bnz_w(MSARegister wt, Label* L) {
bnz_w(wt, shifted_branch_offset(L));
}
void bnz_d(MSARegister wt, int16_t offset);
inline void bnz_d(MSARegister wt, Label* L) {
bnz_d(wt, shifted_branch_offset(L));
}
void ld_b(MSARegister wd, const MemOperand& rs);
void ld_h(MSARegister wd, const MemOperand& rs);
void ld_w(MSARegister wd, const MemOperand& rs);
void ld_d(MSARegister wd, const MemOperand& rs);
void st_b(MSARegister wd, const MemOperand& rs);
void st_h(MSARegister wd, const MemOperand& rs);
void st_w(MSARegister wd, const MemOperand& rs);
void st_d(MSARegister wd, const MemOperand& rs);
void ldi_b(MSARegister wd, int32_t imm10);
void ldi_h(MSARegister wd, int32_t imm10);
void ldi_w(MSARegister wd, int32_t imm10);
void ldi_d(MSARegister wd, int32_t imm10);
void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_s_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_s_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_u_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_u_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_u_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void maxi_u_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_s_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_s_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_u_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_u_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_u_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void mini_u_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void ceqi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void ceqi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void ceqi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void ceqi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_s_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_s_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_u_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_u_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_u_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void clti_u_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_s_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_s_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_u_b(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_u_h(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_u_w(MSARegister wd, MSARegister ws, uint32_t imm5);
void clei_u_d(MSARegister wd, MSARegister ws, uint32_t imm5);
void andi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void ori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void nori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void xori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void bmnzi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void bmzi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void bseli_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void shf_b(MSARegister wd, MSARegister ws, uint32_t imm8);
void shf_h(MSARegister wd, MSARegister ws, uint32_t imm8);
void shf_w(MSARegister wd, MSARegister ws, uint32_t imm8);
void and_v(MSARegister wd, MSARegister ws, MSARegister wt);
void or_v(MSARegister wd, MSARegister ws, MSARegister wt);
void nor_v(MSARegister wd, MSARegister ws, MSARegister wt);
void xor_v(MSARegister wd, MSARegister ws, MSARegister wt);
void bmnz_v(MSARegister wd, MSARegister ws, MSARegister wt);
void bmz_v(MSARegister wd, MSARegister ws, MSARegister wt);
void bsel_v(MSARegister wd, MSARegister ws, MSARegister wt);
void fill_b(MSARegister wd, Register rs);
void fill_h(MSARegister wd, Register rs);
void fill_w(MSARegister wd, Register rs);
void fill_d(MSARegister wd, Register rs);
void pcnt_b(MSARegister wd, MSARegister ws);
void pcnt_h(MSARegister wd, MSARegister ws);
void pcnt_w(MSARegister wd, MSARegister ws);
void pcnt_d(MSARegister wd, MSARegister ws);
void nloc_b(MSARegister wd, MSARegister ws);
void nloc_h(MSARegister wd, MSARegister ws);
void nloc_w(MSARegister wd, MSARegister ws);
void nloc_d(MSARegister wd, MSARegister ws);
void nlzc_b(MSARegister wd, MSARegister ws);
void nlzc_h(MSARegister wd, MSARegister ws);
void nlzc_w(MSARegister wd, MSARegister ws);
void nlzc_d(MSARegister wd, MSARegister ws);
void fclass_w(MSARegister wd, MSARegister ws);
void fclass_d(MSARegister wd, MSARegister ws);
void ftrunc_s_w(MSARegister wd, MSARegister ws);
void ftrunc_s_d(MSARegister wd, MSARegister ws);
void ftrunc_u_w(MSARegister wd, MSARegister ws);
void ftrunc_u_d(MSARegister wd, MSARegister ws);
void fsqrt_w(MSARegister wd, MSARegister ws);
void fsqrt_d(MSARegister wd, MSARegister ws);
void frsqrt_w(MSARegister wd, MSARegister ws);
void frsqrt_d(MSARegister wd, MSARegister ws);
void frcp_w(MSARegister wd, MSARegister ws);
void frcp_d(MSARegister wd, MSARegister ws);
void frint_w(MSARegister wd, MSARegister ws);
void frint_d(MSARegister wd, MSARegister ws);
void flog2_w(MSARegister wd, MSARegister ws);
void flog2_d(MSARegister wd, MSARegister ws);
void fexupl_w(MSARegister wd, MSARegister ws);
void fexupl_d(MSARegister wd, MSARegister ws);