From 31154a5611e4e2367ec7e468af02d2b47e790a30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Zasso?= Date: Sat, 17 Apr 2021 16:28:40 +0200 Subject: [PATCH] deps: V8: cherry-pick 516b5d3f9cfe Original commit message: Merged: [wasm-simd][x64] Check for register when emitting shuffles Some shuffles take have either register or memory operand for second input, but the codegen incorrectly assumes that it is always a register. Bug: v8:10824 (cherry picked from commit ddf30bea13902829eeb71aa0ec747155e27e5a68) Change-Id: I897c4290a8b91ff2ab839e98b16a9696c0bae511 No-Try: true No-Presubmit: true No-Tree-Checks: true Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2391280 Reviewed-by: Bill Budge Commit-Queue: Zhi An Ng Cr-Commit-Position: refs/branch-heads/8.6@{#6} Cr-Branched-From: a64aed2333abf49e494d2a5ce24bbd14fff19f60-refs/heads/8.6.395@{#1} Cr-Branched-From: a626bc036236c9bf92ac7b87dc40c9e538b087e3-refs/heads/master@{#69472} Refs: https://github.com/v8/v8/commit/516b5d3f9cfe5cfe78cf38cce0069f8f3d211e7c PR-URL: https://github.com/nodejs/node/pull/38275 Reviewed-By: Matteo Collina Reviewed-By: Jiawen Geng Reviewed-By: Shelley Vohr --- common.gypi | 2 +- deps/v8/src/codegen/x64/assembler-x64.h | 4 ++++ .../src/compiler/backend/x64/code-generator-x64.cc | 12 ++++++++---- deps/v8/test/cctest/test-disasm-x64.cc | 1 + 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/common.gypi b/common.gypi index 1e05129315c2de..9d9c830b3d0c8c 100644 --- a/common.gypi +++ b/common.gypi @@ -36,7 +36,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.29', + 'v8_embedder_string': '-node.30', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/src/codegen/x64/assembler-x64.h b/deps/v8/src/codegen/x64/assembler-x64.h index 24eb9765782f21..c1c4194f9c3745 100644 --- a/deps/v8/src/codegen/x64/assembler-x64.h +++ b/deps/v8/src/codegen/x64/assembler-x64.h @@ -1562,6 +1562,10 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG); emit(imm8); } + void vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) { + vinstr(0x0F, dst, src1, src2, k66, k0F3A, kWIG); + emit(imm8); + } void vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2); void vps(byte op, XMMRegister dst, XMMRegister src1, Operand src2); diff --git a/deps/v8/src/compiler/backend/x64/code-generator-x64.cc b/deps/v8/src/compiler/backend/x64/code-generator-x64.cc index 4f99ad49ba8980..e32a98e78fc157 100644 --- a/deps/v8/src/compiler/backend/x64/code-generator-x64.cc +++ b/deps/v8/src/compiler/backend/x64/code-generator-x64.cc @@ -579,10 +579,14 @@ void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen, ASSEMBLE_SIMD_INSTR(opcode, dst, input_index); \ } while (false) -#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm) \ - do { \ - DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \ - __ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \ +#define ASSEMBLE_SIMD_IMM_SHUFFLE(opcode, imm) \ + do { \ + DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0)); \ + if (instr->InputAt(1)->IsSimd128Register()) { \ + __ opcode(i.OutputSimd128Register(), i.InputSimd128Register(1), imm); \ + } else { \ + __ opcode(i.OutputSimd128Register(), i.InputOperand(1), imm); \ + } \ } while (false) #define ASSEMBLE_SIMD_ALL_TRUE(opcode) \ diff --git a/deps/v8/test/cctest/test-disasm-x64.cc b/deps/v8/test/cctest/test-disasm-x64.cc index 8e9eadca25e94b..290a57653a68a7 100644 --- a/deps/v8/test/cctest/test-disasm-x64.cc +++ b/deps/v8/test/cctest/test-disasm-x64.cc @@ -813,6 +813,7 @@ TEST(DisasmX64) { __ vpblendw(xmm1, xmm2, xmm3, 23); __ vpblendw(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 23); __ vpalignr(xmm1, xmm2, xmm3, 4); + __ vpalignr(xmm1, xmm2, Operand(rbx, rcx, times_4, 10000), 4); __ vblendvpd(xmm1, xmm2, xmm3, xmm4);