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deps: V8: cherry-pick 5fe919f78321
Original commit message:

    PPC: clear VXCVI before doing a conversion

    This bit may not get cleared automatically and could show
    results from older executed instructions.

    Change-Id: I5976f9a6c5bf87b1a63ef0f35493b222729e20f6
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3812037
    Reviewed-by: Junliang Yan <junyan@redhat.com>
    Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
    Cr-Commit-Position: refs/heads/main@{#82237}

Refs: v8/v8@5fe919f
PR-URL: #45587
Reviewed-By: Michael Dawson <midawson@redhat.com>
Reviewed-By: Jiawen Geng <technicalcute@gmail.com>
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richardlau committed Jan 17, 2023
1 parent d375242 commit 8dce62c
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Showing 2 changed files with 5 additions and 1 deletion.
2 changes: 1 addition & 1 deletion common.gypi
Expand Up @@ -36,7 +36,7 @@

# Reset this number to 0 on major V8 upgrades.
# Increment by one for each non-official patch applied to deps/v8.
'v8_embedder_string': '-node.21',
'v8_embedder_string': '-node.22',

##### V8 defaults for Node.js #####

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4 changes: 4 additions & 0 deletions deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h
Expand Up @@ -1455,6 +1455,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
fcmpu(src.fp(), kScratchDoubleReg);
bunordered(trap);

mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
fctiwz(kScratchDoubleReg, src.fp());
MovDoubleLowToInt(dst.gp(), kScratchDoubleReg);
mcrfs(cr7, VXCVI);
Expand All @@ -1463,6 +1464,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
}
case kExprI32UConvertF64:
case kExprI32UConvertF32: {
mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
ConvertDoubleToUnsignedInt64(src.fp(), r0, kScratchDoubleReg,
kRoundToZero);
mcrfs(cr7, VXCVI); // extract FPSCR field containing VXCVI into cr7
Expand All @@ -1478,6 +1480,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
fcmpu(src.fp(), kScratchDoubleReg);
bunordered(trap);

mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
fctidz(kScratchDoubleReg, src.fp());
MovDoubleToInt64(dst.gp(), kScratchDoubleReg);
mcrfs(cr7, VXCVI);
Expand All @@ -1490,6 +1493,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode,
fcmpu(src.fp(), kScratchDoubleReg);
bunordered(trap);

mtfsb0(VXCVI); // clear FPSCR:VXCVI bit
fctiduz(kScratchDoubleReg, src.fp());
MovDoubleToInt64(dst.gp(), kScratchDoubleReg);
mcrfs(cr7, VXCVI);
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