From 8dce62c7fe56206dd8f6c111c7aaa05f9f98d615 Mon Sep 17 00:00:00 2001 From: Richard Lau Date: Tue, 22 Nov 2022 10:15:39 -0500 Subject: [PATCH] deps: V8: cherry-pick 5fe919f78321 Original commit message: PPC: clear VXCVI before doing a conversion This bit may not get cleared automatically and could show results from older executed instructions. Change-Id: I5976f9a6c5bf87b1a63ef0f35493b222729e20f6 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3812037 Reviewed-by: Junliang Yan Commit-Queue: Milad Farazmand Cr-Commit-Position: refs/heads/main@{#82237} Refs: https://github.com/v8/v8/commit/5fe919f783214c978cb174425554ede8fc1eac5f PR-URL: https://github.com/nodejs/node/pull/45587 Reviewed-By: Michael Dawson Reviewed-By: Jiawen Geng --- common.gypi | 2 +- deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/common.gypi b/common.gypi index f3e47909677639..5372c8d42de531 100644 --- a/common.gypi +++ b/common.gypi @@ -36,7 +36,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.21', + 'v8_embedder_string': '-node.22', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h b/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h index 796ddaa4d17385..31ce3e5a8f407d 100644 --- a/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h +++ b/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc.h @@ -1455,6 +1455,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, fcmpu(src.fp(), kScratchDoubleReg); bunordered(trap); + mtfsb0(VXCVI); // clear FPSCR:VXCVI bit fctiwz(kScratchDoubleReg, src.fp()); MovDoubleLowToInt(dst.gp(), kScratchDoubleReg); mcrfs(cr7, VXCVI); @@ -1463,6 +1464,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, } case kExprI32UConvertF64: case kExprI32UConvertF32: { + mtfsb0(VXCVI); // clear FPSCR:VXCVI bit ConvertDoubleToUnsignedInt64(src.fp(), r0, kScratchDoubleReg, kRoundToZero); mcrfs(cr7, VXCVI); // extract FPSCR field containing VXCVI into cr7 @@ -1478,6 +1480,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, fcmpu(src.fp(), kScratchDoubleReg); bunordered(trap); + mtfsb0(VXCVI); // clear FPSCR:VXCVI bit fctidz(kScratchDoubleReg, src.fp()); MovDoubleToInt64(dst.gp(), kScratchDoubleReg); mcrfs(cr7, VXCVI); @@ -1490,6 +1493,7 @@ bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, fcmpu(src.fp(), kScratchDoubleReg); bunordered(trap); + mtfsb0(VXCVI); // clear FPSCR:VXCVI bit fctiduz(kScratchDoubleReg, src.fp()); MovDoubleToInt64(dst.gp(), kScratchDoubleReg); mcrfs(cr7, VXCVI);