From c04e1df396d1ca971a4af31682b7009ce652f132 Mon Sep 17 00:00:00 2001 From: Luigi Pinca Date: Tue, 22 Nov 2022 14:57:10 +0100 Subject: [PATCH] Revert "deps: fix zlib compilation for CPUs without SIMD features" This reverts commit 26991f795d2f111de40366187720e2f71e701d88. PR-URL: https://github.com/nodejs/node/pull/45589 Fixes: https://github.com/nodejs/node/issues/32856 Reviewed-By: Richard Lau Reviewed-By: Yagiz Nizipli --- deps/zlib/adler32_simd.c | 4 ---- deps/zlib/crc32_simd.c | 4 ---- deps/zlib/crc_folding.c | 12 ------------ 3 files changed, 20 deletions(-) diff --git a/deps/zlib/adler32_simd.c b/deps/zlib/adler32_simd.c index d79b3886a230a1..58966eecf0b800 100644 --- a/deps/zlib/adler32_simd.c +++ b/deps/zlib/adler32_simd.c @@ -50,13 +50,9 @@ #define NMAX 5552 #if defined(ADLER32_SIMD_SSSE3) -#ifndef __GNUC__ -#define __attribute__() -#endif #include -__attribute__((target("ssse3"))) uint32_t ZLIB_INTERNAL adler32_simd_( /* SSSE3 */ uint32_t adler, const unsigned char *buf, diff --git a/deps/zlib/crc32_simd.c b/deps/zlib/crc32_simd.c index 1181e0f9f2c07d..d80beba39c0397 100644 --- a/deps/zlib/crc32_simd.c +++ b/deps/zlib/crc32_simd.c @@ -8,9 +8,6 @@ #include "crc32_simd.h" #if defined(CRC32_SIMD_SSE42_PCLMUL) -#ifndef __GNUC__ -#define __attribute__() -#endif /* * crc32_sse42_simd_(): compute the crc32 of the buffer, where the buffer @@ -24,7 +21,6 @@ #include #include -__attribute__((target("sse4.2,pclmul"))) uint32_t ZLIB_INTERNAL crc32_sse42_simd_( /* SSE4.2+PCLMUL */ const unsigned char *buf, z_size_t len, diff --git a/deps/zlib/crc_folding.c b/deps/zlib/crc_folding.c index 4e9c6e78529f7e..ee31d4918d6413 100644 --- a/deps/zlib/crc_folding.c +++ b/deps/zlib/crc_folding.c @@ -25,10 +25,6 @@ #include #include -#ifndef __GNUC__ -#define __attribute__() -#endif - #define CRC_LOAD(s) \ do { \ __m128i xmm_crc0 = _mm_loadu_si128((__m128i *)s->crc0 + 0);\ @@ -45,7 +41,6 @@ _mm_storeu_si128((__m128i *)s->crc0 + 4, xmm_crc_part);\ } while (0); -__attribute__((target("sse4.2,pclmul"))) ZLIB_INTERNAL void crc_fold_init(deflate_state *const s) { CRC_LOAD(s) @@ -60,7 +55,6 @@ ZLIB_INTERNAL void crc_fold_init(deflate_state *const s) s->strm->adler = 0; } -__attribute__((target("sse4.2,pclmul"))) local void fold_1(deflate_state *const s, __m128i *xmm_crc0, __m128i *xmm_crc1, __m128i *xmm_crc2, __m128i *xmm_crc3) @@ -87,7 +81,6 @@ local void fold_1(deflate_state *const s, *xmm_crc3 = _mm_castps_si128(ps_res); } -__attribute__((target("sse4.2,pclmul"))) local void fold_2(deflate_state *const s, __m128i *xmm_crc0, __m128i *xmm_crc1, __m128i *xmm_crc2, __m128i *xmm_crc3) @@ -122,7 +115,6 @@ local void fold_2(deflate_state *const s, *xmm_crc3 = _mm_castps_si128(ps_res31); } -__attribute__((target("sse4.2,pclmul"))) local void fold_3(deflate_state *const s, __m128i *xmm_crc0, __m128i *xmm_crc1, __m128i *xmm_crc2, __m128i *xmm_crc3) @@ -163,7 +155,6 @@ local void fold_3(deflate_state *const s, *xmm_crc3 = _mm_castps_si128(ps_res32); } -__attribute__((target("sse4.2,pclmul"))) local void fold_4(deflate_state *const s, __m128i *xmm_crc0, __m128i *xmm_crc1, __m128i *xmm_crc2, __m128i *xmm_crc3) @@ -230,7 +221,6 @@ local const unsigned zalign(32) pshufb_shf_table[60] = { 0x0201008f,0x06050403,0x0a090807,0x0e0d0c0b /* shl 1 (16 -15)/shr15*/ }; -__attribute__((target("sse4.2,pclmul"))) local void partial_fold(deflate_state *const s, const size_t len, __m128i *xmm_crc0, __m128i *xmm_crc1, __m128i *xmm_crc2, __m128i *xmm_crc3, @@ -281,7 +271,6 @@ local void partial_fold(deflate_state *const s, const size_t len, *xmm_crc3 = _mm_castps_si128(ps_res); } -__attribute__((target("sse4.2,pclmul"))) ZLIB_INTERNAL void crc_fold_copy(deflate_state *const s, unsigned char *dst, const unsigned char *src, long len) { @@ -438,7 +427,6 @@ local const unsigned zalign(16) crc_mask2[4] = { 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; -__attribute__((target("sse4.2,pclmul"))) unsigned ZLIB_INTERNAL crc_fold_512to32(deflate_state *const s) { const __m128i xmm_mask = _mm_load_si128((__m128i *)crc_mask);