diff --git a/common.gypi b/common.gypi index 537be24c2fabe0..155f02fe420383 100644 --- a/common.gypi +++ b/common.gypi @@ -36,7 +36,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.13', + 'v8_embedder_string': '-node.15', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/src/execution/riscv64/simulator-riscv64.cc b/deps/v8/src/execution/riscv64/simulator-riscv64.cc index 479c4b6a2fc898..5b45f0a36dae78 100644 --- a/deps/v8/src/execution/riscv64/simulator-riscv64.cc +++ b/deps/v8/src/execution/riscv64/simulator-riscv64.cc @@ -127,6 +127,164 @@ static inline bool is_overlapped_widen(const int astart, int asize, #define require_align(val, pos) CHECK_EQ(is_aligned(val, pos), true) #endif +// RVV +// The following code about RVV was based from: +// https://github.com/riscv/riscv-isa-sim +// Copyright (c) 2010-2017, The Regents of the University of California +// (Regents). All Rights Reserved. + +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// 3. Neither the name of the Regents nor the +// names of its contributors may be used to endorse or promote products +// derived from this software without specific prior written permission. + +// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, +// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF +// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +template +struct type_usew_t; +template <> +struct type_usew_t<8> { + using type = uint8_t; +}; + +template <> +struct type_usew_t<16> { + using type = uint16_t; +}; + +template <> +struct type_usew_t<32> { + using type = uint32_t; +}; + +template <> +struct type_usew_t<64> { + using type = uint64_t; +}; + +template <> +struct type_usew_t<128> { + using type = __uint128_t; +}; +template +struct type_sew_t; + +template <> +struct type_sew_t<8> { + using type = int8_t; +}; + +template <> +struct type_sew_t<16> { + using type = int16_t; +}; + +template <> +struct type_sew_t<32> { + using type = int32_t; +}; + +template <> +struct type_sew_t<64> { + using type = int64_t; +}; + +template <> +struct type_sew_t<128> { + using type = __int128_t; +}; + +#define VV_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VV_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VX_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VX_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type rs1 = (type_usew_t::type)(get_register(rs1_reg())); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_UPARAMS(x) \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ + type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VN_PARAMS(x) \ + constexpr int half_x = x >> 1; \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type uimm5 = (type_sew_t::type)(instr_.RvvUimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VN_UPARAMS(x) \ + constexpr int half_x = x >> 1; \ + type_usew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VXI_PARAMS(x) \ + type_sew_t::type& vd = \ + Rvvelt::type>(rvv_vd_reg(), i, true); \ + type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ + type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); \ + type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ + type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); + +#define VI_XI_SLIDEDOWN_PARAMS(x, off) \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i + off); + +#define VI_XI_SLIDEUP_PARAMS(x, offset) \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i - offset); + +/* Vector Integer Extension */ +#define VI_VIE_PARAMS(x, scale) \ + if ((x / scale) < 8) UNREACHABLE(); \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + +#define VI_VIE_UPARAMS(x, scale) \ + if ((x / scale) < 8) UNREACHABLE(); \ + auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ + auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); + #define require_noover(astart, asize, bstart, bsize) \ CHECK_EQ(!is_overlapped(astart, asize, bstart, bsize), true) #define require_noover_widen(astart, asize, bstart, bsize) \ diff --git a/deps/v8/src/execution/riscv64/simulator-riscv64.h b/deps/v8/src/execution/riscv64/simulator-riscv64.h index 4d2cd460c4b70b..bf1dda48e9d1fd 100644 --- a/deps/v8/src/execution/riscv64/simulator-riscv64.h +++ b/deps/v8/src/execution/riscv64/simulator-riscv64.h @@ -652,164 +652,6 @@ class Simulator : public SimulatorBase { } } - // RVV - // The following code about RVV was based from: - // https://github.com/riscv/riscv-isa-sim - // Copyright (c) 2010-2017, The Regents of the University of California - // (Regents). All Rights Reserved. - - // Redistribution and use in source and binary forms, with or without - // modification, are permitted provided that the following conditions are met: - // 1. Redistributions of source code must retain the above copyright - // notice, this list of conditions and the following disclaimer. - // 2. Redistributions in binary form must reproduce the above copyright - // notice, this list of conditions and the following disclaimer in the - // documentation and/or other materials provided with the distribution. - // 3. Neither the name of the Regents nor the - // names of its contributors may be used to endorse or promote products - // derived from this software without specific prior written permission. - - // IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - // SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, - // ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - // REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - // REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED - // TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - // PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - // HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - // MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - template - struct type_usew_t; - template <> - struct type_usew_t<8> { - using type = uint8_t; - }; - - template <> - struct type_usew_t<16> { - using type = uint16_t; - }; - - template <> - struct type_usew_t<32> { - using type = uint32_t; - }; - - template <> - struct type_usew_t<64> { - using type = uint64_t; - }; - - template <> - struct type_usew_t<128> { - using type = __uint128_t; - }; - template - struct type_sew_t; - - template <> - struct type_sew_t<8> { - using type = int8_t; - }; - - template <> - struct type_sew_t<16> { - using type = int16_t; - }; - - template <> - struct type_sew_t<32> { - using type = int32_t; - }; - - template <> - struct type_sew_t<64> { - using type = int64_t; - }; - - template <> - struct type_sew_t<128> { - using type = __int128_t; - }; - -#define VV_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VV_UPARAMS(x) \ - type_usew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_usew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ - type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VX_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VX_UPARAMS(x) \ - type_usew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_usew_t::type rs1 = (type_usew_t::type)(get_register(rs1_reg())); \ - type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VI_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VI_UPARAMS(x) \ - type_usew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ - type_usew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VN_PARAMS(x) \ - constexpr int half_x = x >> 1; \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type uimm5 = (type_sew_t::type)(instr_.RvvUimm5()); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VN_UPARAMS(x) \ - constexpr int half_x = x >> 1; \ - type_usew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_usew_t::type uimm5 = (type_usew_t::type)(instr_.RvvUimm5()); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VXI_PARAMS(x) \ - type_sew_t::type& vd = \ - Rvvelt::type>(rvv_vd_reg(), i, true); \ - type_sew_t::type vs1 = Rvvelt::type>(rvv_vs1_reg(), i); \ - type_sew_t::type vs2 = Rvvelt::type>(rvv_vs2_reg(), i); \ - type_sew_t::type rs1 = (type_sew_t::type)(get_register(rs1_reg())); \ - type_sew_t::type simm5 = (type_sew_t::type)(instr_.RvvSimm5()); - -#define VI_XI_SLIDEDOWN_PARAMS(x, off) \ - auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ - auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i + off); - -#define VI_XI_SLIDEUP_PARAMS(x, offset) \ - auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ - auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i - offset); - -/* Vector Integer Extension */ -#define VI_VIE_PARAMS(x, scale) \ - if ((x / scale) < 8) UNREACHABLE(); \ - auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ - auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - -#define VI_VIE_UPARAMS(x, scale) \ - if ((x / scale) < 8) UNREACHABLE(); \ - auto& vd = Rvvelt::type>(rvv_vd_reg(), i, true); \ - auto vs2 = Rvvelt::type>(rvv_vs2_reg(), i); - inline void rvv_trace_vd() { if (::v8::internal::FLAG_trace_sim) { __int128_t value = Vregister_[rvv_vd_reg()]; diff --git a/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.cc b/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.cc index cc527a5432e195..dda2104feb3d1d 100644 --- a/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.cc +++ b/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.cc @@ -23,10 +23,10 @@ namespace internal { * This assembler uses the following register assignment convention * - s3 : kScratchReg. Temporarily stores the index of capture start after a matching pass * for a global regexp. - * - a5 : Pointer to current Code object including heap object tag. - * - a6 : Current position in input, as negative offset from end of string. + * - s4 : Pointer to current Code object including heap object tag. + * - s1 : Current position in input, as negative offset from end of string. * Please notice that this is the byte offset, not the character offset! - * - a7 : Currently loaded character. Must be loaded using + * - s2 : Currently loaded character. Must be loaded using * LoadCurrentCharacter before using any of the dispatch methods. * - t0 : Points to tip of backtrack stack * - t1 : Unused. diff --git a/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.h b/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.h index 4692b6781416c8..121569849a6778 100644 --- a/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.h +++ b/deps/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.h @@ -155,10 +155,10 @@ class V8_EXPORT_PRIVATE RegExpMacroAssemblerRISCV // Register holding the current input position as negative offset from // the end of the string. - static constexpr Register current_input_offset() { return a6; } + static constexpr Register current_input_offset() { return s1; } // The register containing the current character after LoadCurrentCharacter. - static constexpr Register current_character() { return a7; } + static constexpr Register current_character() { return s2; } // Register holding address of the end of the input string. static constexpr Register end_of_input_address() { return t2; } @@ -172,7 +172,7 @@ class V8_EXPORT_PRIVATE RegExpMacroAssemblerRISCV static constexpr Register backtrack_stackpointer() { return t0; } // Register holding pointer to the current code object. - static constexpr Register code_pointer() { return a5; } + static constexpr Register code_pointer() { return s4; } // Byte size of chars in the string to match (decided by the Mode argument). inline int char_size() const { return static_cast(mode_); }