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How to let OpenVino recoginze Intel Agilex® 7 Device #3876

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lhf552004 opened this issue Nov 27, 2023 · 11 comments
Open

How to let OpenVino recoginze Intel Agilex® 7 Device #3876

lhf552004 opened this issue Nov 27, 2023 · 11 comments

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@lhf552004
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Hi, I created a test.py, to verify the device can be recoginized by OpenVino.

from openvino.runtime import Core

# Initialize OpenVINO runtime
ie = Core()
available_devices = ie.available_devices
print(available_devices)

The result is below.

(openvino_env) sadmin@desktop-pc:~/dev/project-ASR$ python3 test.py 
[E:] [BSL] found 0 ioexpander device
['CPU', 'GNA']

I don't know which plugin is for that in the document below.
https://docs.openvino.ai/2021.4/openvino_docs_IE_DG_Device_Plugins.html

The OpenVino runtime I installed is Openvino 2022.3.1.
I'm stuck at it for three weeks, please help me.
@Wovchena
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Hi. There's no FPGA plugin in OpenVINO package. I think you should use something like https://www.intel.com/content/www/us/en/docs/programmable/768977/2023-2-1/inference-on-image-classification-graphs.html. I'm not familiar with that thing. @eamonma, can you help?

@lhf552004
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lhf552004 commented Dec 1, 2023 •
edited

Thanks @Wovchena. I've run the demo from the doc. It seems work with image rather than audio. Meanwhile the device name is not shown in the available_devices.
Here is the log.
Meanwhile, I found the demo works with speech model. But it cannot recognize the device either.

https://github.com/openvinotoolkit/open_model_zoo/tree/master/demos/speech_recognition_wav2vec_demo/python
@eamonma, can you help have a look?

I appreciate it.

yawen@yawen-desktop-pc:~/dev/project-ASR$ DLA_PLUGINS_XML_FILE=$COREDLA_WORK/runtime/plugins.xml \
>   DLA_ARCH_FILE=$curarch \
>   python $COREDLA_WORK/runtime/python_demos/OpenVINO_benchmark_app/benchmark_app.py \
>     -b=1 \
>     -m $xmldir/wav2vec2-base/FP32/wav2vec2-base.xml \
>    -d=HETERO:FPGA,CPU \
>    -niter=8 \
>    -api=async \
>    -nireq=4 \
>    -i $imagedir \
> 
[Step 1/11] Parsing and validating input arguments
[ INFO ] Parsing input parameters
args:
Namespace(api_type='async', batch_size='1', cache_dir='', data_shape='', dump_config='', exec_graph_path=None, extensions=None, infer_precision=None, infer_threads_pinning=None, inference_only=None, input_mean='', input_output_precision=None, input_precision=None, input_scale='', latency_percentile=50, layout='', load_config='', number_infer_requests=4, number_iterations=8, number_streams=None, number_threads=None, output_precision=None, path_to_cldnn_config=None, path_to_model='/home/yawen/dev/project-ASR/demo/models/public//wav2vec2-base/FP32/wav2vec2-base.xml', paths_to_input=[['/home/yawen/dev/project-ASR/demo/sample_audios']], pcseq=False, perf_counts=False, perf_counts_sort='', perf_hint='', report_folder='', report_type=None, shape='', target_device='HETERO:FPGA,CPU', time=None)
[Step 2/11] Loading OpenVINO Runtime
[ INFO ] OpenVINO:
[ INFO ] Build ................................. 2022.3.1-9227-cf2c7da5689-releases/2022/3
[ INFO ] 
[ INFO ] Device info:
[ INFO ] CPU
[ INFO ] Build ................................. 2022.3.1-9227-cf2c7da5689-releases/2022/3
[ INFO ] FPGA
[ INFO ] Build ................................. custom_build
[ INFO ] HETERO
[ INFO ] Build ................................. CoreDLA2023r1Custom
[ INFO ] 
[ INFO ] 
[Step 3/11] Setting device configuration
[ WARNING ] Performance hint was not explicitly specified in command line. Device(CPU) performance hint will be set to THROUGHPUT.
[Step 4/11] Reading model files
[ INFO ] Loading model files
[ INFO ] Read model took 153.50 ms
[ INFO ] Original model I/O parameters:
[ INFO ] Model inputs:
[ INFO ]     inputs (node: inputs) : f32 / [N,S] / [1,30480]
[ INFO ] Model outputs:
[ INFO ]     logits (node: logits) : f32 / [...] / [1,95,32]
[Step 5/11] Resizing model to match image sizes and given batch
[ INFO ] Model batch size: 1
[Step 6/11] Configuring input of the model
[ INFO ] Model inputs:
[ INFO ]     inputs (node: inputs) : f32 / [N,S] / [1,30480]
[ INFO ] Model outputs:
[ INFO ]     logits (node: logits) : f32 / [...] / [1,95,32]
[Step 7/11] Loading the model to the device
[ INFO ] The input graph is split into 1 subgraph(s), CPU:1.
[ INFO ] Compile model took 1409.77 ms
[Step 8/11] Querying optimal runtime parameters
[ INFO ] Model:
[ INFO ]   NETWORK_NAME: main_graph
[ INFO ]   OPTIMAL_NUMBER_OF_INFER_REQUESTS: 1
[ INFO ]   EXECUTION_DEVICES: ['CPU']
[ INFO ]   TARGET_FALLBACK: FPGA,CPU
[ INFO ]   MULTI_DEVICE_PRIORITIES: FPGA,CPU
[ INFO ]   HETERO_DUMP_GRAPH_DOT: True
[ INFO ]   EXCLUSIVE_ASYNC_REQUESTS: True
[ INFO ]   CACHE_DIR: 
[ INFO ]   CPU_BIND_THREAD: YES
[ INFO ]   CPU_THREADS_NUM: 0
[ INFO ]   CPU_THROUGHPUT_STREAMS: 1
[ INFO ]   DUMP_EXEC_GRAPH_AS_DOT: 
[ INFO ]   DYN_BATCH_ENABLED: NO
[ INFO ]   DYN_BATCH_LIMIT: 0
[ INFO ]   ENFORCE_BF16: NO
[ INFO ]   PERFORMANCE_HINT: THROUGHPUT
[ INFO ]   PERFORMANCE_HINT_NUM_REQUESTS: 4
[ INFO ]   PERF_COUNT: NO
[Step 9/11] Creating infer requests and preparing input tensors
[ WARNING ] This files has unsupported extensions and will be ignored: ['/home/yawen/dev/project-ASR/demo/sample_audios/harvard_mono.wav', '/home/yawen/dev/project-ASR/demo/sample_audios/sample_mono.wav'].
Supported extentions:
Images: ['.jpeg', '.jpg', '.png', '.bmp']
Binary: ['.bin']
[ WARNING ] No input files were given for input 'inputs'!. This input will be filled with random values!
[ INFO ] Fill input 'inputs' with random values 
[Step 10/11] Measuring performance (Start inference asynchronously, 4 inference requests, limits: 8 iterations)
[ INFO ] Benchmarking in inference only mode (inputs filling are not included in measurement loop).
[ INFO ] First inference took 92.54 ms
[Step 11/11] Dumping statistics report
[ INFO ] Execution Devices:['CPU']
[ INFO ] Count:            8 iterations
[ INFO ] Duration:         474.71 ms
[ INFO ] Latency:
[ INFO ]    Median:        224.53 ms
[ INFO ]    Average:       193.80 ms
[ INFO ]    Min:           70.54 ms
[ INFO ]    Max:           247.58 m

Here I tried the device HETERO:FPGA. And it is not recognized unfortunately.

(openvino_env) yawen@yawen-desktop-pc:~/dev/project-ASR/demo/open_model_zoo/demos/speech_recognition_wav2vec_demo/python$ python3 speech_recognition_wav2vec_demo.py -m /home/yawen/dev/project-ASR/demo/models/public/wav2vec2-base/FP16/wav2vec2-base.xml -i /home/yawen/dev/project-ASR/demo/sample_audios/harvard_mono.wav -d 'HETERO:FPGA'
[ INFO ] OpenVINO Runtime
[ INFO ]        build: 2022.3.1-9227-cf2c7da5689-releases/2022/3
[ INFO ] Reading model /home/yawen/dev/project-ASR/demo/models/public/wav2vec2-base/FP16/wav2vec2-base.xml
model inputs: [<Output: names[inputs] shape[1,30480] type: f32>]
Traceback (most recent call last):
  File "speech_recognition_wav2vec_demo.py", line 151, in <module>
    sys.exit(main() or 0)
  File "speech_recognition_wav2vec_demo.py", line 141, in main
    model = Wav2Vec(core, args.model, audio.shape, args.device, args.vocab, args.dynamic_shape)
  File "speech_recognition_wav2vec_demo.py", line 77, in __init__
    compiled_model = core.compile_model(model, device)
  File "/opt/intel/openvino_2022.3.1/python/python3.8/openvino/runtime/ie_api.py", line 399, in compile_model
    super().compile_model(model, device_name, {} if config is None else config),
RuntimeError: Device with "FPGA" name is not registered in the OpenVINO Runtime

@domi-papoi
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Device HETERO:FPGA doesn't work, hetero means at least 2 devices. The reason it doesn't run on FPGA is that your model or any layer within is not supported by the FPGA, see:
[Step 7/11] Loading the model to the device
[ INFO ] The input graph is split into 1 subgraph(s), CPU:1.
That means all will run on CPU due to layers not supported on FPGA.
You can run dla_compiler to see an output form the performance analysis and you can have an output of the graph with which layers are run on what device (CPU or FPGA) on the .svg file.
Hope this helps!

@lhf552004
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Hi Thanks, @domi-papoi , here is the output of running dla_compiler

yawen@yawen-desktop-pc:~$ cd $COREDLA_WORK/demo/models/public/resnet-50-tf/FP32
yawen@yawen-desktop-pc:~/dev/project-ASR/demo/models/public/resnet-50-tf/FP32$             dla_compiler \
>             --march $COREDLA_ROOT/example_architectures/AGX7_Performance.arch \
>             --network-file ./resnet-50-tf.xml \
>             --foutput-format=open_vino_hetero \
>             --o $COREDLA_WORK/demo/RN50_Performance_b1.bin \
>             --batch-size=1 \
>             --fanalyze-performance
network-weightings not specified. Auto assigning network weights to 1.0
Model path set to ./resnet-50-tf.xml
read_graph for resnet-50-tf complete.
[ INFO ] The input graph is split into 1 subgraph(s), FPGA:1.
Starting compilation
Finished compilation in 6976 ms
Exporting input transform to file
Exporting output transform to file
Executing performance estimate
Estimating performance
----------------------------------------------------------------
resnet-50-tf_0 reported throughput: 145.878394
TOTAL DDR SPACE REQUIRED = 53.365479 MB
      DDR CONFIG BUFFER SIZE = 0.055664 MB
      DDR FILTER BUFFER SIZE = 49.437744 MB
      DDR INTERMEDIATE BUFFER SIZE = 3.062500 MB
TOTAL DDR TRANSFERS REQUIRED = 70.911682 MB
      DDR FILTER READS REQUIRED   = 52.792969 MB
      DDR FEATURE READS REQUIRED  = 11.170471 MB
      DDR FEATURE WRITES REQUIRED = 6.892578 MB
NUMBER OF DDR FEATURE READS = 13.000000
MINIMUM AVERAGE DDR BANDWIDTH REQUIRED = 10344.482329 MB/s

----------------------------------------------------------------
Performance Estimator Throughput Breakdown
Arch: kvec64xcvec32_i5x1_fp13agx_sb32768_xbark32_actk32_poolk4
Number of DLA instances                          = 1
Number of DDR Banks per DLA instance             = 1
CoreDLA Target Fmax                              = 400 MHz
PE Target Fmax                                   = 400 MHz
Batch Size                                       = 1
PE-only Conv Throughput No DDR                   = 163 fps
PE-only Conv Throughput                          = 153 fps
Overall Throughput Inf PE Buf Depth (zero MPBW)  = 152 fps
Overall Throughput Zero PE Buf Depth (zero MPBW) = 151 fps
Overall Throughput Inf PE Buf Depth              = 146 fps
Overall Throughput Zero PE Buf Depth             = 145 fps
----------------------------------------------------------------
FINAL THROUGHPUT = 145.878 fps
FINAL THROUGHPUT PER FMAX (CoreDLA) = 0.364696 fps/MHz
FINAL THROUGHPUT PER FMAX (PE)      = 0.364696 fps/MHz
Performance Estimator Execution Time: 2 ms

Meanwhile, I found an issue, when checking "aocl diagnose all". Is it related to aocl, or the bitstream I programmed into FPGA?

yawen@yawen-desktop-pc:~$ aocl diagnose all
--------------------------------------------------------------------
ICD System Diagnostics                                              
--------------------------------------------------------------------

Using the following location for ICD installation: 
	/etc/OpenCL/vendors

Found 3 icd entry at that location:
	/etc/OpenCL/vendors/Intel_FPGA_SSG_Emulator.icd
	/etc/OpenCL/vendors/intel64.icd
	/etc/OpenCL/vendors/Altera.icd

The following OpenCL libraries are referenced in the icd files:
	/opt/intel//oneapi/compiler/latest/lib/libintelocl_emu.so
	/opt/intel//oneapi/compiler/latest/lib/libintelocl.so
	/opt/intel//oneapi/compiler/latest/opt/oclfpga/host/linux64/lib/libalteracl.so

Checking LD_LIBRARY_PATH for registered libraries:
	/opt/intel//oneapi/compiler/latest/opt/oclfpga/host/linux64/lib/libalteracl.so was registered on the system.

Using the following location for fcd installations:
	/opt/Intel/OpenCL/Boards

Found 1 fcd entry at that location:
	/opt/Intel/OpenCL/Boards/de10_agilex.fcd

The following OpenCL libraries are referenced in the fcd files:
	/home/yawen/Downloads/DE10_Agilex_revC_linux_BSP_21.2/de10_agilex/linux64/lib/libterasic_agilex_mmd.so

Checking LD_LIBRARY_PATH for registered libraries:
	/home/yawen/Downloads/DE10_Agilex_revC_linux_BSP_21.2/de10_agilex/linux64/lib/libterasic_agilex_mmd.so was registered on the system.

Number of Platforms = 1 
	1. Intel(R) FPGA SDK for OpenCL(TM)                             | Intel(R) Corporation           | OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 2024.0
--------------------------------------------------------------------
ICD diagnostics PASSED                                              
--------------------------------------------------------------------
--------------------------------------------------------------------
BSP Diagnostics                                                     
--------------------------------------------------------------------
  HAL Kern: Version mismatch! Expected 0xa0c00001 but read 0x4130
Hardware version ID differs from version expected by software.  Either:
   a) Ensure your compiled design was generated by the same ACL build
      currently in use, OR
   b) The host can not communicate with the compiled kernel.
diagnose: acl_kernel_if.cpp:655: int acl_kernel_if_init(acl_kernel_if*, acl_bsp_io, acl_system_def_t*): Assertion `0' failed.

@domi-papoi
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Looks like you had a previous installation of oneAPI, that may interfere with FPGA AI Suite. Follow the install instructions from here after you uninstall the oneAPI https://www.intel.com/content/www/us/en/docs/programmable/768970/2023-3/additional-software-prerequisites-for-51059.html

@lhf552004
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lhf552004 commented Dec 2, 2023 •
edited

Thanks, the mismatch issue is gone, and the output shows DIAGNOSTIC_PASSED. However, there is an error in the output:
ICD diagnostics FAILED. Is it related to the OpenVino-not-recoginzied-FPGA-device issue?

yawen@yawen-desktop-pc:~$ aocl diagnose acl0
--------------------------------------------------------------------
ICD System Diagnostics                                              
--------------------------------------------------------------------

Using the following location for ICD installation: 
	/etc/OpenCL/vendors

ERROR: No ICD entry at that location.  Without ICD and FCD, host executables
must be linked directly to Intel FPGA runtime (libalteracl.so) and BSP MMD
library instead of to the Khronos ICD library (libOpenCL.so).
	To use ICD, please reinstall the Intel OpenCL SDK.
--------------------------------------------------------------------
ICD diagnostics FAILED                                              
--------------------------------------------------------------------
--------------------------------------------------------------------
BSP Diagnostics                                                     
--------------------------------------------------------------------
Using Device with name: B2E2_8GBx4 : Agilex Reference Platform (aclde10_agilex0)
Using Device from vendor: Terasic
clGetDeviceInfo CL_DEVICE_GLOBAL_MEM_SIZE = 34359737344
clGetDeviceInfo CL_DEVICE_MAX_MEM_ALLOC_SIZE = 34359737344
Allocated 34359737344 bytes
Actual maximum buffer size = 34359737344 bytes
Writing 32767 MB to global memory ...
Allocated 1073741824 Bytes host buffer for large transfers
Write speed: 7967.99 MB/s [7345.93 -> 8470.53]
Reading and verifying 32767 MB from global memory ...
Read speed: 8657.40 MB/s [7995.21 -> 9244.38]
Successfully wrote and readback 32767 MB buffer

Transferring 262144 KBs in 512 512 KB blocks ... 2264.51 MB/s
Transferring 262144 KBs in 256 1024 KB blocks ... 3317.94 MB/s
Transferring 262144 KBs in 128 2048 KB blocks ... 5064.50 MB/s
Transferring 262144 KBs in 64 4096 KB blocks ... 6371.19 MB/s
Transferring 262144 KBs in 32 8192 KB blocks ... 7482.06 MB/s
Transferring 262144 KBs in 16 16384 KB blocks ... 8187.99 MB/s
Transferring 262144 KBs in 8 32768 KB blocks ... 8532.18 MB/s
Transferring 262144 KBs in 4 65536 KB blocks ... 8879.99 MB/s
Transferring 262144 KBs in 2 131072 KB blocks ... 7915.55 MB/s
Transferring 262144 KBs in 1 262144 KB blocks ... 8149.83 MB/s

As a reference:
PCIe Gen1 peak speed: 250MB/s/lane
PCIe Gen2 peak speed: 500MB/s/lane
PCIe Gen3 peak speed: 985MB/s/lane

Writing 262144 KBs with block size (in bytes) below:

Block_Size Avg    Max    Min    End-End (MB/s)
  524288 1769.41 1934.26 1459.05 1734.51
 1048576 2305.57 2758.35 1473.52 2263.10
 2097152 3235.07 4436.01 2397.21 3196.03
 4194304 4655.27 5852.16 3458.18 4625.04
 8388608 5369.79 6699.56 4100.70 5322.08
16777216 5995.18 7350.42 4839.13 5977.27
33554432 6645.95 7686.03 5855.43 6637.53
67108864 6773.44 7722.54 6115.21 6769.50
134217728 7600.26 7915.55 7309.13 7597.92
268435456 7071.89 7071.89 7071.89 7071.89

Reading 262144 KBs with block size (in bytes) below:

Block_Size Avg    Max    Min    End-End (MB/s)
  524288 1628.45 2264.51 1035.71 1593.36
 1048576 2438.71 3317.94 1986.73 2392.87
 2097152 3527.83 5064.50 2625.23 3490.07
 4194304 5288.06 6371.19 3640.35 5253.33
 8388608 5729.86 7482.06 4383.56 5686.46
16777216 7185.98 8187.99 5910.32 7169.38
33554432 7599.60 8532.18 6541.38 7589.46
67108864 7709.63 8879.99 6752.80 7705.38
134217728 7779.24 7786.15 7772.35 7777.01
268435456 8149.83 8149.83 8149.83 8149.83

Write top speed = 7915.55 MB/s
Read top speed = 8879.99 MB/s
Throughput = 8397.77 MB/s

DIAGNOSTIC_PASSED


yawen@yawen-desktop-pc:~$ aocl version
aocl 22.4.0.49.1 (Intel(R) FPGA SDK for OpenCL(TM), Version 22.4.0 Build 49.1 Pro Edition, Copyright (c) 2022 Intel Corporation)
yawen@yawen-desktop-pc:~$ uname -r
5.15.0-89-generic
yawen@yawen-desktop-pc:~$ uname -v
#99~20.04.1-Ubuntu SMP Thu Nov 2 15:16:47 UTC 2023
yawen@yawen-desktop-pc:~$ quartus --version

OpenVINO Runtime version: 2022.3.1-9227-cf2c7da5689-releases/2022/3

(openvino_env) yawen@yawen-desktop-pc:~/dev/project-ASR/src/test$ pip list | grep openvino-dev
openvino-dev                 2022.3.0

Quartus Prime Design Software
Version 22.4.0 Build 94 12/07/2022 SC Pro Edition
Copyright (C) 2022  Intel Corporation. All rights reserved.

FPGA-AI-suite version is fpga_ai_suite_2023.2.1

The interesting thing is the version is installed for "Intel® FPGA RTE for OpenCL" is 21.2. But it showed as 22.4, which is the same with quartus.

@domi-papoi
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ICD failure is not related to OpenVINO, most likely you're missing an fcd or icd file, not critical for FPGA AI Suite.
Some OpenCL paths are overwritten by the Quartus 22.4 install, not an issue.
Now if you run the resnet 50 model after you program the FPGA it should run on FPGA.

@lhf552004
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lhf552004 commented Dec 2, 2023 •
edited

Thanks for explanation.
The resnet-50-tf.xml model seems OK by dla_compiler.
However, the available devices still don't contain FPGA.

(openvino_env) yawen@yawen-desktop-pc:~/dev/project-ASR/demo/models/public/resnet-50-tf/FP32$ dla_compiler \
>             --march $COREDLA_ROOT/example_architectures/AGX7_Performance.arch \
>             --network-file ./resnet-50-tf.xml \
>             --foutput-format=open_vino_hetero \
>             --o $COREDLA_WORK/demo/RN50_Performance_b1.bin \
>             --batch-size=1 \
>             --fanalyze-performance
network-weightings not specified. Auto assigning network weights to 1.0
Model path set to ./resnet-50-tf.xml
read_graph for resnet-50-tf complete.
[ INFO ] The input graph is split into 1 subgraph(s), FPGA:1.
Starting compilation
Finished compilation in 6695 ms
Exporting input transform to file
Exporting output transform to file
Executing performance estimate
Estimating performance
----------------------------------------------------------------
resnet-50-tf_0 reported throughput: 145.878394
TOTAL DDR SPACE REQUIRED = 53.365479 MB
      DDR CONFIG BUFFER SIZE = 0.055664 MB
      DDR FILTER BUFFER SIZE = 49.437744 MB
      DDR INTERMEDIATE BUFFER SIZE = 3.062500 MB
TOTAL DDR TRANSFERS REQUIRED = 70.911682 MB
      DDR FILTER READS REQUIRED   = 52.792969 MB
      DDR FEATURE READS REQUIRED  = 11.170471 MB
      DDR FEATURE WRITES REQUIRED = 6.892578 MB
NUMBER OF DDR FEATURE READS = 13.000000
MINIMUM AVERAGE DDR BANDWIDTH REQUIRED = 10344.482329 MB/s

----------------------------------------------------------------
Performance Estimator Throughput Breakdown
Arch: kvec64xcvec32_i5x1_fp13agx_sb32768_xbark32_actk32_poolk4
Number of DLA instances                          = 1
Number of DDR Banks per DLA instance             = 1
CoreDLA Target Fmax                              = 400 MHz
PE Target Fmax                                   = 400 MHz
Batch Size                                       = 1
PE-only Conv Throughput No DDR                   = 163 fps
PE-only Conv Throughput                          = 153 fps
Overall Throughput Inf PE Buf Depth (zero MPBW)  = 152 fps
Overall Throughput Zero PE Buf Depth (zero MPBW) = 151 fps
Overall Throughput Inf PE Buf Depth              = 146 fps
Overall Throughput Zero PE Buf Depth             = 145 fps
----------------------------------------------------------------
FINAL THROUGHPUT = 145.878 fps
FINAL THROUGHPUT PER FMAX (CoreDLA) = 0.364696 fps/MHz
FINAL THROUGHPUT PER FMAX (PE)      = 0.364696 fps/MHz
Performance Estimator Execution Time: 2 ms

from openvino.runtime import Core

core = Core()

available_devices = core.available_devices
print(available_devices)

(openvino_env) yawen@yawen-desktop-pc:~/dev/project-ASR/src/test$ python3 test4.py 
[E:] [BSL] found 0 ioexpander device
['CPU', 'GNA']

(openvino_env) yawen@yawen-desktop-pc:~/dev/project-ASR/demo/open_model_zoo/demos/speech_recognition_wav2vec_demo/python$ python3 speech_recognition_wav2vec_demo.py -m /home/yawen/dev/project-ASR/demo/models/public/wav2vec2-base/FP16/wav2vec2-base.xml -i /home/yawen/dev/project-ASR/demo/sample_audios/how_are_you_doing_today.wav -d 'HETERO:FPGA'
[ INFO ] OpenVINO Runtime
[ INFO ]        build: 2022.3.1-9227-cf2c7da5689-releases/2022/3
[ INFO ] Reading model /home/yawen/dev/project-ASR/demo/models/public/wav2vec2-base/FP16/wav2vec2-base.xml
model inputs: [<Output: names[inputs] shape[1,30480] type: f32>]
Traceback (most recent call last):
  File "speech_recognition_wav2vec_demo.py", line 151, in <module>
    sys.exit(main() or 0)
  File "speech_recognition_wav2vec_demo.py", line 141, in main
    model = Wav2Vec(core, args.model, audio.shape, args.device, args.vocab, args.dynamic_shape)
  File "speech_recognition_wav2vec_demo.py", line 77, in __init__
    compiled_model = core.compile_model(model, device)
  File "/opt/intel/openvino_2022.3.1/python/python3.8/openvino/runtime/ie_api.py", line 399, in compile_model
    super().compile_model(model, device_name, {} if config is None else config),
RuntimeError: Device with "FPGA" name is not registered in the OpenVINO Runtime

@domi-papoi
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Available devices is fixed in latest version of openVINO, @Wovchena can we back port the fix to OpenVINO 2022.3? Not sure how critical is this @lhf552004

@lhf552004
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That’s great to hear that. The reason I install version 2022 is because FPGA ai suite 2023 require openvino 2022. Is it necessary to install fpga ai suite for recognizing fpga device?

@Wovchena
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Wovchena commented Dec 4, 2023

Available devices is fixed in latest version of openVINO, @Wovchena can we back port the fix to OpenVINO 2022.3? Not sure how critical is this @lhf552004

@domi-papoi, I'm the wrong person to ask. Anyway, you can try opening the backporting PR and see what happens.

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@domi-papoi @lhf552004 @Wovchena