{"payload":{"pageCount":2,"repositories":[{"type":"Public","name":"libriscv","owner":"agra-uni-bremen","isFork":false,"description":"Extensible implementation of the RISC-V ISA based on FreeMonads","topicNames":["simulation","free-monads","formal-specification","riscv-v"],"topicsNotShown":0,"allTopics":["simulation","free-monads","formal-specification","riscv-v"],"primaryLanguage":{"name":"Haskell","color":"#5e5086"},"pullRequestCount":0,"issueCount":0,"starsCount":4,"forksCount":1,"license":"MIT License","participation":[0,0,0,0,7,7,0,6,0,0,1,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,17,22,0,0,1,1,12],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-28T08:17:55.349Z"}},{"type":"Public","name":"BinSym","owner":"agra-uni-bremen","isFork":false,"description":"Symbolic execution for RISC-V machine code based on the formal LibRISCV ISA model","topicNames":["symbolic-execution","riscv","program-analysis","riscv32"],"topicsNotShown":0,"allTopics":["symbolic-execution","riscv","program-analysis","riscv32"],"primaryLanguage":{"name":"Haskell","color":"#5e5086"},"pullRequestCount":0,"issueCount":0,"starsCount":31,"forksCount":3,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-24T07:28:49.723Z"}},{"type":"Public","name":"symsysc-experiments","owner":"agra-uni-bremen","isFork":false,"description":"Experiments and DUTs for SymSysC repo","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":1,"license":null,"participation":[1,0,1,0,0,0,0,0,0,0,1,0,0,0,1,1,0,0,1,0,0,0,0,0,0,0,0,3,0,0,0,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-22T09:15:51.637Z"}},{"type":"Public","name":"SymSysC","owner":"agra-uni-bremen","isFork":false,"description":"Symbolic Execution of SystemC TLM Peripherals","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":1,"license":null,"participation":[1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-22T09:08:31.801Z"}},{"type":"Public","name":"guix-symex","owner":"agra-uni-bremen","isFork":false,"description":"A Guix channel for reproducible symbolic execution research","topicNames":["reproducible-research","symbolic-execution","guix","software-testing","klee"],"topicsNotShown":0,"allTopics":["reproducible-research","symbolic-execution","guix","software-testing","klee"],"primaryLanguage":{"name":"Scheme","color":"#1e4aec"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"GNU General Public License v3.0","participation":[0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,22,21,6,0,3,6,0,0,0,1,0,0,3,1,0,3,3],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-22T08:39:07.535Z"}},{"type":"Public","name":"microrv32","owner":"agra-uni-bremen","isFork":false,"description":"SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Scala","color":"#c22d40"},"pullRequestCount":0,"issueCount":0,"starsCount":35,"forksCount":4,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-06T07:31:52.317Z"}},{"type":"Public","name":"opt-vp","owner":"agra-uni-bremen","isFork":false,"description":"Virtual Prototype for identifying Application Specific Hardware Optimization candidates","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":0,"license":"MIT License","participation":[0,0,0,0,0,0,1,0,0,0,0,0,0,0,5,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,1,1,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-10T13:17:18.917Z"}},{"type":"Public","name":"opt-seq","owner":"agra-uni-bremen","isFork":false,"description":"An algorithm to merge RISC-V instruction sequences","topicNames":["asic","embedded-systems","risc-v","virtual-prototyping","hardware-optimization"],"topicsNotShown":0,"allTopics":["asic","embedded-systems","risc-v","virtual-prototyping","hardware-optimization"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":2,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-03-06T21:46:13.180Z"}},{"type":"Public","name":"riscv-vp","owner":"agra-uni-bremen","isFork":true,"description":"RISC-V Virtual Prototype","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":3,"issueCount":11,"starsCount":132,"forksCount":61,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-01-10T09:52:57.708Z"}},{"type":"Public","name":"vp-integration-tests","owner":"agra-uni-bremen","isFork":false,"description":"Tests for peripherals and other utilities of the riscv-vp","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-01-10T09:33:57.105Z"}},{"type":"Public","name":"symex_processor_verification","owner":"agra-uni-bremen","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":2,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-12-06T13:57:30.220Z"}},{"type":"Public","name":"crave","owner":"agra-uni-bremen","isFork":false,"description":"Constrained random stimuli generation for C++ and SystemC","topicNames":["constrained-random","systemc"],"topicsNotShown":0,"allTopics":["constrained-random","systemc"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":11,"starsCount":45,"forksCount":13,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-11-29T18:03:29.990Z"}},{"type":"Public","name":"vlsid2024-inputaware-approxadders-magic","owner":"agra-uni-bremen","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-10-19T08:08:30.640Z"}},{"type":"Public","name":"JxCDC2022-imagin-add","owner":"agra-uni-bremen","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-10-05T16:12:39.990Z"}},{"type":"Public","name":"symex-vp","owner":"agra-uni-bremen","isFork":false,"description":"A concolic testing engine for RISC-V embedded software with support for SystemC peripherals","topicNames":["symbolic-execution","systemc","risc-v","klee","concolic-execution","riscv32","concolic-testing","riscv"],"topicsNotShown":0,"allTopics":["symbolic-execution","systemc","risc-v","klee","concolic-execution","riscv32","concolic-testing","riscv"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":18,"forksCount":5,"license":"GNU General Public License v3.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-10-04T07:53:59.861Z"}},{"type":"Public","name":"tcasii2022-maradiv-lib","owner":"agra-uni-bremen","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-10-02T16:21:18.089Z"}},{"type":"Public","name":"newcas2023-magic-multiplier-lib","owner":"agra-uni-bremen","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-08-03T14:53:06.313Z"}},{"type":"Public","name":"icee2022-magic-adder-lib","owner":"agra-uni-bremen","isFork":false,"description":"Artifacts of the paper: \"Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-Based Memristor Design Style\"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-08-03T14:34:48.938Z"}},{"type":"Public","name":"formal-iss","owner":"agra-uni-bremen","isFork":false,"description":"Generate an ISS for riscv-vp from a formal LibRISCV ISA model","topicNames":["simulation","code-generation","risc-v","formal-specification","riscv32","unparser"],"topicsNotShown":0,"allTopics":["simulation","code-generation","risc-v","formal-specification","riscv32","unparser"],"primaryLanguage":{"name":"Haskell","color":"#5e5086"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-07-13T12:24:13.588Z"}},{"type":"Public","name":"spike-libriscv","owner":"agra-uni-bremen","isFork":false,"description":"Spike RISC-V simulator but with a autogenerated LibRISCV backend","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":1,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-07-10T09:24:20.434Z"}},{"type":"Public","name":"libriscv-vp","owner":"agra-uni-bremen","isFork":false,"description":"RISC-V Virtual Prototype with ISS generated from LibRISCV","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":1,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-07-10T09:23:07.893Z"}},{"type":"Public","name":"clover","owner":"agra-uni-bremen","isFork":false,"description":"A library for concolic execution of RV32 instruction set simulators","topicNames":["symbolic-execution","risc-v","klee","concolic-testing"],"topicsNotShown":0,"allTopics":["symbolic-execution","risc-v","klee","concolic-testing"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":1,"forksCount":1,"license":"GNU General Public License v3.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-07-06T15:03:26.339Z"}},{"type":"Public","name":"virtual-breadboard","owner":"agra-uni-bremen","isFork":false,"description":"Virtual Breadboard / PCB simulation for Prototyping and Educational Purposes","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":5,"starsCount":6,"forksCount":2,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-04T15:52:42.062Z"}},{"type":"Public","name":"sifive-hifive1","owner":"agra-uni-bremen","isFork":false,"description":"This Repo contains documentation to the HiFive1 Board along with some example programs.","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":0,"issueCount":0,"starsCount":2,"forksCount":2,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-04-04T16:13:01.799Z"}},{"type":"Public","name":"systemc","owner":"agra-uni-bremen","isFork":true,"description":"SystemC Reference Implementation","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":138,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-03-27T09:33:12.636Z"}},{"type":"Public","name":"hardbound-vp","owner":"agra-uni-bremen","isFork":false,"description":"Virtual Prototype with symbolic execution support and HardBound path analyzer","topicNames":["symbolic-execution","memory-safety","systemc","virtual-prototyping","hardbound"],"topicsNotShown":0,"allTopics":["symbolic-execution","memory-safety","systemc","virtual-prototyping","hardbound"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":1,"license":"GNU General Public License v3.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-02-14T12:53:22.742Z"}},{"type":"Public","name":"virtual-bus","owner":"agra-uni-bremen","isFork":false,"description":"Simple protocol to connect two memory mapped buses (e.g. for Hardware In The Loop)","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":1,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-02-02T15:45:23.030Z"}},{"type":"Public","name":"virtual-breadboard-protocol","owner":"agra-uni-bremen","isFork":false,"description":"Protocol definitions for SoC Environment simultations.","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-01-13T14:53:50.215Z"}},{"type":"Public","name":"sps-vp","owner":"agra-uni-bremen","isFork":false,"description":"Fork of SymEx-VP for specification-based symbolic execution of stateful network protocol implementations via SPS protocol specifications","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"GNU General Public License v3.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-01-09T11:31:36.017Z"}},{"type":"Public","name":"sps","owner":"agra-uni-bremen","isFork":false,"description":"Scheme library to specify network protocol state machines","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"Scheme","color":"#1e4aec"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-01-09T09:13:56.946Z"}}],"repositoryCount":55,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}