axi_sim_mem write after read leads to AXI error

[christian-lanius]

Hi,
I use the axi_sim_mem to model off-chip memory. If write and read at the same address happens in quick succession, AXI handshaking is not being followed:
Once RVALID goes high, the RDATA has to be stable if RREADY is low. So if the read data is stalling and the write happens, the RDATA is being updated with the new value. Xilinx protocol checker will flag this as an error:

BIT( 62) : ERROR : AXI_ERRS_RDATA_STABLE: RDATA must remain stable when RVALID is asserted and RREADY low. Spec: section A3.2.1.

Here is the simulation view:

The error occurs at the red cursor, slightly before that, the data changes even though RVALID is high and RREADY is low. The read has been triggered at the start of the shown sequence (ID 0C from address 02135a20). Because later a write to the same address is performed, the error occurs.

While AXI does not have any ordering between reads and writes (both of the values are acceptable output values), however they have to be stable.

[vborchsh]

Hi,

The same thing here. Are there any update or workaround on it?

Thanks

PS. Just for history: you need to clarify timescale values in whole your project