{"payload":{"header_redesign_enabled":false,"results":[{"id":"129229399","archived":false,"color":"#DAE1C2","followers":958,"has_funding_file":false,"hl_name":"pulp-platform/axi","hl_trunc_description":"AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication","language":"SystemVerilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":129229399,"name":"axi","owner_id":14332106,"owner_login":"pulp-platform","updated_at":"2024-05-27T15:37:37.739Z","has_issues":true}},"sponsorable":false,"topics":["asic","fpga","hardware","rtl","ip","systemverilog","axi","network-on-chip","axi4","axi4-lite"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":62,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Apulp-platform%252Faxi%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/pulp-platform/axi/star":{"post":"H3NmDfeX04V2-VkIpuDre1K7Bm5Y0dF6zXfMrza8ZLRLzDWTtiyJ_uUGLifSLXRfqoIzkNRnuEhMtdWJGi8dGA"},"/pulp-platform/axi/unstar":{"post":"VGpEWL9Slvz3rPJ-5mbQsE7LnJhEQb00D6O4UnX1-vn646ss_cTl3J8hzLE10S5QYqKDxzy0GfcEsRJShCGHlQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"gTeLFAmQC8Ve3zojxkTQmi-kWK9fCVaoa7xJf5JOtqvoTjBy15YPMYL9Co-1ed8grbDfhtCVBTXDymOzmPvHvA"}}},"title":"Repository search results"}