Repeat register multiple times

[SzymonHitachi]

Hi, Is there any way to repeat a register with multiple fields defined, multiple times in an spreadsheet instead of specifying each one separately?

[taichi-ishitani]

Can you give me example register map?

[SzymonHitachi]

[SzymonHitachi]

I would rather specify the register once and multiply it instead of copy pasting

[taichi-ishitani]

For this purpose, you can use the array register feature.
You need to put its array size to the size cell (column D) like the example below.

For the above example, the memmap register has 3 sub elements and these offset addresses are:

• memmap[0]: 0x00
• memmap[1]: 0x04
• memmap[2]: 0x08

[SzymonHitachi]

Oh nice that works great. Too bad that in VHDL it creates a 1-D port instead of 2-D array like in SV.

[taichi-ishitani]

Too bad that in VHDL it creates a 1-D port instead of 2-D array like in SV.

I don't know how to define 2-D array port because I'm not familiar with VHDL.
How can I do that?

[SzymonHitachi]

Oh. I would contribute if I would have known ruby 😄

In VHDL you need to define a whole type to be able to create array. This means you need to create a VHDL package (similar to SV package) and inside you need to define an array type for that port (or use some global defined port for all rggen ideally)

so for example in rggen_rtl package you can create an array type

type rggen_array is array (integer range <>) of std_logic_vector;

The above is called an unconstrained array -> it needs size provided during instantiation
and then you could define a port when generating

data_out : out rggen_array(0 to 15)(15 downto 0);

[taichi-ishitani]

Thank you for your adovice!

type rggen_array is array (integer range <>) of std_logic_vector;

Can I use this type definition for any version of VHDL?