Improvement Ideas

[cookacounty]

• "Reserved Register" - A register type that would exist for documentation purposes only. For example we have a register field we want to define but it lives in a different place for design specific reasons.
• Simplified verilog output plug-in (flat hierarchy) - Maybe for a reduced set of registers just allow a simple flat view
• Allow additional columns in the excel that show up in the markdown (basically allow custom user fields for documentation)

Some lower priority ideas:

• Allow assignment to just specify bit width for each field, automatically partition the bits based on that
• SRDL output - Looks like someone already suggested this

[taichi-ishitani]

@cookacounty ,
Thank you for your feedback!

Reserved Register

OK. I will add this register type.

Simplified verilog output plug-in (flat hierarchy)

Can you explain more details?
You want to remove generate if blocks?
https://github.com/rggen/rggen-verilog/blob/9adb37688d4b9ddd66514fada4fe3ccf2cfc2426/sample/block_0.v#L147

Allow additional columns in the excel

You can add description of a bit field to column K like below.

Then, values on column K will be put to comment column like below.

Is this suitable for your purpose?

assignment to just specify bit width for each field

Register map written in JSON/Ruby/TOML/YAML supports this feature but xlsx does not.
To support this feature on XLSX register map, we need to change notation of bit assignment (swap positions of lsb and width) or introduce a new notation to specify width only.

SRDL output

Is SRDL SystemRDL?
If yes, I plant to support SystemRDL input but not output.
What is purpose of SystemRDL output?

[cookacounty]

Thanks for the reply! In response to the flat verilog I will try to write some code examples tomorrow. Basically think of an extremely simple implementation of each register field.

For the comment column I was thinking more if you added additional columns those would just get considered as user columns and also show up in the .md (for example if I added some nots in column L of your screenshot)

What is purpose of SystemRDL output?

For the SystemRDL we just have a tool that interprets it. Its the probably the most "industry" standard format for registers I've seen.

To support this feature on XLSX register map, we need to change notation of bit assignment (swap positions of lsb and width) or introduce a new notation to specify width only.

The bit widths - yes I was thinking maybe a different form of notation. If you look at how systemRDL does it, if you specify the WL (word length) it would automatically figure out the index, the same as you addresses are already doing.

[taichi-ishitani]

Basically think of an extremely simple implementation of each register field

I'm interested too!

I added some nots in column L of your screenshot

To do this, you need to create your own plugin.
However, I have not yet written documents to show how to create your own plugin in English. I will try.

we just have a tool that interprets it.

What kind of outputs can your tool generate? C header file? HTML?
If generated outputs are used commonly I need to enhance RgGen.

Its the probably the most "industry" standard format for registers I've seen.

Yes. Therefore, I'm developing SystemRDL parser but I'm not sure that SystemRDL support is needed to increase users.
What do you think?

we need to change notation of bit assignment (swap positions of lsb and width)

I think it is more useful that the first element of the notation is width than LSB position.
I will swap the first element.

[taichi-ishitani]

I've created enhancement tickets for reserved register type (#72) and bit assignment notation without width (#73).

[taichi-ishitani]

@cookacounty
I released RgGen v0.25.0. This release includes new features based on your feedback.
Thank you for your ideas! 😄

[dpryvd]

Suggested register type: Read With Trigger output. Needed to build clear on read statistics counters. I dont see a method to have register return a counter value (read only) and clear that counter which would need to be external. A trigger signal associated with the read could be used for clearing the counter.

A nice option here would be to have the trigger output be a toggle signal, that is toggled each read, allowing an easy clock domain synchronizer that could then drive the external counter clear..

[taichi-ishitani]

Hi @dpryvd ,
Thank you for your suggestion! I agree with it.
I will add this bit field type.

[taichi-ishitani]

Hi @dpryvd ,
I've released the latest RgGen including your proposal.
https://github.com/rggen/rggen/releases/tag/v0.26.0

[aranzaba]

Hi @taichi-ishitani,

First of allI would like to congratulate you for the nice work.

Concerning the RGGEN pluging for VHDL, what about having an option to implement registers using distributed RAM or BRAM?

Many thanks.

[taichi-ishitani]

https://github.com/rggen/rggen-sample-testbench/blob/5b751e8a542d41da0d0e4b597238d908e78ca019/env/apb_top.sv#L310

This is a example using the external register type.
In this case, the register_15_bus_if is connected with an other CSR block.
You can also connect this interface with a RAM block instead of a CSR block.

[aranzaba]

Thanks a lot @taichi-ishitani. That's great! The example that you provided seems to implement what I was looking for. I will play a bit more with your tool and see if I can build an example using external registers.

[taichi-ishitani]

https://github.com/rggen/rggen/wiki/Specification-for-RgGen-Bus-Interface-Protocol

This wiki describes this bus protocol.
In this protocol, there are two write access types:

• 0b11: write
• 0b01: write posted

This distinction is used to implement a bus adapter module.
You don't need to distinguish them when you implement a RAM wrapper module.

[taichi-ishitani]

Hi @aranzaba ,

I am evaluating the available register map tools to be used in new projects.
I will play a bit more

Can you share the evaluation result?
I'd like to refer it for RgGen development.

[aranzaba]

Sure, I can give you some feedback when I am done with the evaluation.