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Check reserved words #154

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taichi-ishitani opened this issue Jul 20, 2023 · 1 comment
Open

Check reserved words #154

taichi-ishitani opened this issue Jul 20, 2023 · 1 comment
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taichi-ishitani commented Jul 20, 2023 •
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Report an error when a SV/Verilog/VHDL reserved words is specified as a register block/register file/register/bit field name.
This is to avoid a compile error when loading a generated source file.
@taichi-ishitani taichi-ishitani self-assigned this Jul 20, 2023
@taichi-ishitani taichi-ishitani added the enhancement New feature or request label Jul 20, 2023
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Lise of VHDL reserved workds
https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/VHDL-RESERVED-Words

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