[VHDL] Array port

[taichi-ishitani]

Currently, an array port is packed into a bit vector port.
For usability, introduce array types and use these instead of a bit vector type.

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Oh. I would contribute if I would have known ruby 😄

In VHDL you need to define a whole type to be able to create array. This means you need to create a VHDL package (similar to SV package) and inside you need to define an array type for that port (or use some global defined port for all rggen ideally)

so for example in rggen_rtl package you can create an array type

type rggen_array is array (integer range <>) of std_logic_vector;

The above is called an unconstrained array -> it needs size provided during instantiation
and then you could define a port when generating

data_out : out rggen_array(0 to 15)(15 downto 0);

Originally posted by @SzymonHitachi in #194 (reply in thread)