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Supported tools #79

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taichi-ishitani opened this issue May 24, 2021 · 3 comments
Open

Supported tools #79

taichi-ishitani opened this issue May 24, 2021 · 3 comments
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@taichi-ishitani
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taichi-ishitani commented May 24, 2021 •
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Check whether or not following tools support generated CSR modules/RAL packages.

  • Simulation
    • Cadence Xcelium
      • VHDL output
    • Mentor Questa/ModelSim
    • Aldec Riviera-PRO
    • GHDL
  • Synthesis
    • Cadence Genus
    • Lattice
    • Microsemi
    • Efinix
    • Yosis
@taichi-ishitani taichi-ishitani added the help wanted Extra attention is needed label May 24, 2021
@davidp135 davidp135 mentioned this issue Nov 11, 2021
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@taichi-ishitani
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@Cra2yPierr0t has confirmed Yosis can handle Verilog RTL generated by RgGen.
Thank you!

@taichi-ishitani
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taichi-ishitani commented May 30, 2022 •
edited

Confirmed Vivado simulator can handle generated RTL and RAL model.
rggen/rggen-sample-testbench#5

@taichi-ishitani
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Metrics DSim can compile and execute the sample env.
rggen/rggen-sample-testbench#11

taichi-ishitani added a commit that referenced this issue May 15, 2024
@taichi-ishitani
Add Metrics DSim
1fe087b 
(refs #79 (comment))
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