{"payload":{"header_redesign_enabled":false,"results":[{"id":"180550709","archived":false,"color":"#701516","followers":290,"has_funding_file":true,"hl_name":"rggen/rggen","hl_trunc_description":"Code generation tool for control and status registers","language":"Ruby","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":180550709,"name":"rggen","owner_id":29380268,"owner_login":"rggen","updated_at":"2024-05-15T12:33:15.451Z","has_issues":true}},"sponsorable":false,"topics":["asic","fpga","vhdl","eda","rtl","verilog","csr","systemverilog","soc","uvm","ral","axi","amba","apb","register-descriptions","wishbone-bus","uvm-ral-model","uvm-register-model","wiki-documents"],"type":"Public","help_wanted_issues_count":2,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":65,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Arggen%252Frggen%2B%2Blanguage%253ARuby","metadata":null,"csrf_tokens":{"/rggen/rggen/star":{"post":"SpoUHn-g7cpvYpggSrNkkYk-1UlNYBMU8LtKD6rb9xPLNtwpz2i6mdRwEn1EFmig1-VHisDEArXJ40fupU_E4A"},"/rggen/rggen/unstar":{"post":"IQ0eAw-17ChonJs2VKsOiz9ba5__bmxjcuwUcKhw1p52uOkk6U1zxbyUlkMYtAZmsT_YLtEzrwDSgcqz9Yoo5A"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"_BFfs-HATmGVdJQvqpLs7Gzp-eQZaJshGJBf_IH-ty1CejlfsOBGaUScI_wbny53Ajrh4pP_DKWWvcd3mN7A2Q"}}},"title":"Repository search results"}