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liftoff-assembler-ppc.h
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liftoff-assembler-ppc.h
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// Copyright 2017 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef V8_WASM_BASELINE_PPC_LIFTOFF_ASSEMBLER_PPC_H_
#define V8_WASM_BASELINE_PPC_LIFTOFF_ASSEMBLER_PPC_H_
#include "src/base/platform/wrappers.h"
#include "src/codegen/assembler.h"
#include "src/heap/memory-chunk.h"
#include "src/wasm/baseline/liftoff-assembler.h"
#include "src/wasm/simd-shuffle.h"
#include "src/wasm/wasm-objects.h"
namespace v8 {
namespace internal {
namespace wasm {
namespace liftoff {
// half
// slot Frame
// -----+--------------------+---------------------------
// n+3 | parameter n |
// ... | ... |
// 4 | parameter 1 | or parameter 2
// 3 | parameter 0 | or parameter 1
// 2 | (result address) | or parameter 0
// -----+--------------------+---------------------------
// 2 | return addr (lr) |
// 1 | previous frame (fp)|
// 0 | const pool (r28) | if const pool is enabled
// -----+--------------------+ <-- frame ptr (fp) or cp
// -1 | StackFrame::WASM |
// -2 | instance |
// -3 | feedback vector |
// -4 | tiering budget |
// -----+--------------------+---------------------------
// -5 | slot 0 (high) | ^
// -6 | slot 0 (low) | |
// -7 | slot 1 (high) | Frame slots
// -8 | slot 1 (low) | |
// | | v
// -----+--------------------+ <-- stack ptr (sp)
//
//
constexpr int32_t kInstanceOffset =
(FLAG_enable_embedded_constant_pool ? 3 : 2) * kSystemPointerSize;
constexpr int kFeedbackVectorOffset =
(FLAG_enable_embedded_constant_pool ? 4 : 3) * kSystemPointerSize;
constexpr int kTierupBudgetOffset =
(FLAG_enable_embedded_constant_pool ? 5 : 4) * kSystemPointerSize;
inline MemOperand GetHalfStackSlot(int offset, RegPairHalf half) {
int32_t half_offset =
half == kLowWord ? 0 : LiftoffAssembler::kStackSlotSize / 2;
return MemOperand(fp, -kInstanceOffset - offset + half_offset);
}
inline MemOperand GetStackSlot(uint32_t offset) {
return MemOperand(fp, -static_cast<int32_t>(offset));
}
inline MemOperand GetInstanceOperand() { return GetStackSlot(kInstanceOffset); }
inline constexpr Condition ToCondition(LiftoffCondition liftoff_cond) {
switch (liftoff_cond) {
case kEqual:
return eq;
case kUnequal:
return ne;
case kSignedLessThan:
case kUnsignedLessThan:
return lt;
case kSignedLessEqual:
case kUnsignedLessEqual:
return le;
case kSignedGreaterEqual:
case kUnsignedGreaterEqual:
return ge;
case kSignedGreaterThan:
case kUnsignedGreaterThan:
return gt;
}
}
inline constexpr bool UseSignedOp(LiftoffCondition liftoff_cond) {
switch (liftoff_cond) {
case kEqual:
case kUnequal:
case kSignedLessThan:
case kSignedLessEqual:
case kSignedGreaterThan:
case kSignedGreaterEqual:
return true;
case kUnsignedLessThan:
case kUnsignedLessEqual:
case kUnsignedGreaterThan:
case kUnsignedGreaterEqual:
return false;
default:
UNREACHABLE();
}
return false;
}
} // namespace liftoff
int LiftoffAssembler::PrepareStackFrame() {
int offset = pc_offset();
addi(sp, sp, Operand::Zero());
return offset;
}
void LiftoffAssembler::PrepareTailCall(int num_callee_stack_params,
int stack_param_delta) {
Register scratch = ip;
// Push the return address and frame pointer to complete the stack frame.
AddS64(sp, sp, Operand(-2 * kSystemPointerSize), r0);
LoadU64(scratch, MemOperand(fp, kSystemPointerSize), r0);
StoreU64(scratch, MemOperand(sp, kSystemPointerSize), r0);
LoadU64(scratch, MemOperand(fp), r0);
StoreU64(scratch, MemOperand(sp), r0);
// Shift the whole frame upwards.
int slot_count = num_callee_stack_params + 2;
for (int i = slot_count - 1; i >= 0; --i) {
LoadU64(scratch, MemOperand(sp, i * kSystemPointerSize), r0);
StoreU64(scratch,
MemOperand(fp, (i - stack_param_delta) * kSystemPointerSize), r0);
}
// Set the new stack and frame pointer.
AddS64(sp, fp, Operand(-stack_param_delta * kSystemPointerSize), r0);
Pop(r0, fp);
mtlr(r0);
}
void LiftoffAssembler::AlignFrameSize() {}
void LiftoffAssembler::PatchPrepareStackFrame(
int offset, SafepointTableBuilder* safepoint_table_builder) {
int frame_size =
GetTotalFrameSize() -
(FLAG_enable_embedded_constant_pool ? 3 : 2) * kSystemPointerSize;
Assembler patching_assembler(
AssemblerOptions{},
ExternalAssemblerBuffer(buffer_start_ + offset, kInstrSize + kGap));
if (V8_LIKELY(frame_size < 4 * KB)) {
patching_assembler.addi(sp, sp, Operand(-frame_size));
return;
}
// The frame size is bigger than 4KB, so we might overflow the available stack
// space if we first allocate the frame and then do the stack check (we will
// need some remaining stack space for throwing the exception). That's why we
// check the available stack space before we allocate the frame. To do this we
// replace the {__ sub(sp, sp, framesize)} with a jump to OOL code that does
// this "extended stack check".
//
// The OOL code can simply be generated here with the normal assembler,
// because all other code generation, including OOL code, has already finished
// when {PatchPrepareStackFrame} is called. The function prologue then jumps
// to the current {pc_offset()} to execute the OOL code for allocating the
// large frame.
// Emit the unconditional branch in the function prologue (from {offset} to
// {pc_offset()}).
int jump_offset = pc_offset() - offset;
if (!is_int26(jump_offset)) {
bailout(kUnsupportedArchitecture, "branch offset overflow");
return;
}
patching_assembler.b(jump_offset, LeaveLK);
// If the frame is bigger than the stack, we throw the stack overflow
// exception unconditionally. Thereby we can avoid the integer overflow
// check in the condition code.
RecordComment("OOL: stack check for large frame");
Label continuation;
if (frame_size < FLAG_stack_size * 1024) {
Register stack_limit = ip;
LoadU64(stack_limit,
FieldMemOperand(kWasmInstanceRegister,
WasmInstanceObject::kRealStackLimitAddressOffset),
r0);
LoadU64(stack_limit, MemOperand(stack_limit), r0);
AddS64(stack_limit, stack_limit, Operand(frame_size), r0);
CmpU64(sp, stack_limit);
bge(&continuation);
}
Call(wasm::WasmCode::kWasmStackOverflow, RelocInfo::WASM_STUB_CALL);
// The call will not return; just define an empty safepoint.
safepoint_table_builder->DefineSafepoint(this);
if (FLAG_debug_code) stop();
bind(&continuation);
// Now allocate the stack space. Note that this might do more than just
// decrementing the SP; consult {TurboAssembler::AllocateStackSpace}.
SubS64(sp, sp, Operand(frame_size), r0);
// Jump back to the start of the function, from {pc_offset()} to
// right after the reserved space for the {__ sub(sp, sp, framesize)} (which
// is a branch now).
jump_offset = offset - pc_offset() + kInstrSize;
if (!is_int26(jump_offset)) {
bailout(kUnsupportedArchitecture, "branch offset overflow");
return;
}
b(jump_offset, LeaveLK);
}
void LiftoffAssembler::FinishCode() { EmitConstantPool(); }
void LiftoffAssembler::AbortCompilation() { FinishCode(); }
// static
constexpr int LiftoffAssembler::StaticStackFrameSize() {
return liftoff::kTierupBudgetOffset;
}
int LiftoffAssembler::SlotSizeForType(ValueKind kind) {
switch (kind) {
case kS128:
return value_kind_size(kind);
default:
return kStackSlotSize;
}
}
bool LiftoffAssembler::NeedsAlignment(ValueKind kind) {
return (kind == kS128 || is_reference(kind));
}
void LiftoffAssembler::LoadConstant(LiftoffRegister reg, WasmValue value,
RelocInfo::Mode rmode) {
switch (value.type().kind()) {
case kI32:
mov(reg.gp(), Operand(value.to_i32(), rmode));
break;
case kI64:
mov(reg.gp(), Operand(value.to_i64(), rmode));
break;
case kF32: {
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
mov(scratch, Operand(value.to_f32_boxed().get_bits()));
MovIntToFloat(reg.fp(), scratch, ip);
break;
}
case kF64: {
UseScratchRegisterScope temps(this);
Register scratch = temps.Acquire();
mov(scratch, Operand(value.to_f64_boxed().get_bits()));
MovInt64ToDouble(reg.fp(), scratch);
break;
}
default:
UNREACHABLE();
}
}
void LiftoffAssembler::LoadInstanceFromFrame(Register dst) {
LoadU64(dst, liftoff::GetInstanceOperand(), r0);
}
void LiftoffAssembler::LoadFromInstance(Register dst, Register instance,
int offset, int size) {
DCHECK_LE(0, offset);
switch (size) {
case 1:
LoadU8(dst, MemOperand(instance, offset), r0);
break;
case 4:
LoadU32(dst, MemOperand(instance, offset), r0);
break;
case 8:
LoadU64(dst, MemOperand(instance, offset), r0);
break;
default:
UNIMPLEMENTED();
}
}
void LiftoffAssembler::LoadTaggedPointerFromInstance(Register dst,
Register instance,
int offset) {
LoadTaggedPointerField(dst, MemOperand(instance, offset), r0);
}
void LiftoffAssembler::SpillInstance(Register instance) {
StoreU64(instance, liftoff::GetInstanceOperand(), r0);
}
void LiftoffAssembler::ResetOSRTarget() {}
void LiftoffAssembler::LoadTaggedPointer(Register dst, Register src_addr,
Register offset_reg,
int32_t offset_imm,
LiftoffRegList pinned) {
LoadTaggedPointerField(dst, MemOperand(src_addr, offset_reg, offset_imm), r0);
}
void LiftoffAssembler::LoadFullPointer(Register dst, Register src_addr,
int32_t offset_imm) {
LoadU64(dst, MemOperand(src_addr, offset_imm), r0);
}
void LiftoffAssembler::StoreTaggedPointer(Register dst_addr,
Register offset_reg,
int32_t offset_imm,
LiftoffRegister src,
LiftoffRegList pinned,
SkipWriteBarrier skip_write_barrier) {
MemOperand dst_op = MemOperand(dst_addr, offset_reg, offset_imm);
StoreTaggedField(src.gp(), dst_op, r0);
if (skip_write_barrier || FLAG_disable_write_barriers) return;
Label write_barrier;
Label exit;
CheckPageFlag(dst_addr, ip, MemoryChunk::kPointersFromHereAreInterestingMask,
ne, &write_barrier);
b(&exit);
bind(&write_barrier);
JumpIfSmi(src.gp(), &exit);
if (COMPRESS_POINTERS_BOOL) {
DecompressTaggedPointer(src.gp(), src.gp());
}
CheckPageFlag(src.gp(), ip, MemoryChunk::kPointersToHereAreInterestingMask,
eq, &exit);
mov(ip, Operand(offset_imm));
add(ip, ip, dst_addr);
if (offset_reg != no_reg) {
add(ip, ip, offset_reg);
}
CallRecordWriteStubSaveRegisters(dst_addr, ip, RememberedSetAction::kEmit,
SaveFPRegsMode::kSave,
StubCallMode::kCallWasmRuntimeStub);
bind(&exit);
}
void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr,
Register offset_reg, uintptr_t offset_imm,
LoadType type, LiftoffRegList pinned,
uint32_t* protected_load_pc, bool is_load_mem,
bool i64_offset) {
if (!i64_offset && offset_reg != no_reg) {
ZeroExtWord32(ip, offset_reg);
offset_reg = ip;
}
MemOperand src_op = MemOperand(src_addr, offset_reg, offset_imm);
if (protected_load_pc) *protected_load_pc = pc_offset();
switch (type.value()) {
case LoadType::kI32Load8U:
case LoadType::kI64Load8U:
LoadU8(dst.gp(), src_op, r0);
break;
case LoadType::kI32Load8S:
case LoadType::kI64Load8S:
LoadS8(dst.gp(), src_op, r0);
break;
case LoadType::kI32Load16U:
case LoadType::kI64Load16U:
if (is_load_mem) {
LoadU16LE(dst.gp(), src_op, r0);
} else {
LoadU16(dst.gp(), src_op, r0);
}
break;
case LoadType::kI32Load16S:
case LoadType::kI64Load16S:
if (is_load_mem) {
LoadS16LE(dst.gp(), src_op, r0);
} else {
LoadS16(dst.gp(), src_op, r0);
}
break;
case LoadType::kI64Load32U:
if (is_load_mem) {
LoadU32LE(dst.gp(), src_op, r0);
} else {
LoadU32(dst.gp(), src_op, r0);
}
break;
case LoadType::kI32Load:
case LoadType::kI64Load32S:
if (is_load_mem) {
LoadS32LE(dst.gp(), src_op, r0);
} else {
LoadS32(dst.gp(), src_op, r0);
}
break;
case LoadType::kI64Load:
if (is_load_mem) {
LoadU64LE(dst.gp(), src_op, r0);
} else {
LoadU64(dst.gp(), src_op, r0);
}
break;
case LoadType::kF32Load:
if (is_load_mem) {
// `ip` could be used as offset_reg.
Register scratch = ip;
if (offset_reg == ip) {
scratch = GetRegisterThatIsNotOneOf(src_addr);
push(scratch);
}
LoadF32LE(dst.fp(), src_op, r0, scratch);
if (offset_reg == ip) {
pop(scratch);
}
} else {
LoadF32(dst.fp(), src_op, r0);
}
break;
case LoadType::kF64Load:
if (is_load_mem) {
// `ip` could be used as offset_reg.
Register scratch = ip;
if (offset_reg == ip) {
scratch = GetRegisterThatIsNotOneOf(src_addr);
push(scratch);
}
LoadF64LE(dst.fp(), src_op, r0, scratch);
if (offset_reg == ip) {
pop(scratch);
}
} else {
LoadF64(dst.fp(), src_op, r0);
}
break;
case LoadType::kS128Load:
bailout(kUnsupportedArchitecture, "SIMD");
break;
default:
UNREACHABLE();
}
}
void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
uintptr_t offset_imm, LiftoffRegister src,
StoreType type, LiftoffRegList pinned,
uint32_t* protected_store_pc, bool is_store_mem) {
MemOperand dst_op =
MemOperand(dst_addr, offset_reg, offset_imm);
if (protected_store_pc) *protected_store_pc = pc_offset();
switch (type.value()) {
case StoreType::kI32Store8:
case StoreType::kI64Store8:
StoreU8(src.gp(), dst_op, r0);
break;
case StoreType::kI32Store16:
case StoreType::kI64Store16:
if (is_store_mem) {
StoreU16LE(src.gp(), dst_op, r0);
} else {
StoreU16(src.gp(), dst_op, r0);
}
break;
case StoreType::kI32Store:
case StoreType::kI64Store32:
if (is_store_mem) {
StoreU32LE(src.gp(), dst_op, r0);
} else {
StoreU32(src.gp(), dst_op, r0);
}
break;
case StoreType::kI64Store:
if (is_store_mem) {
StoreU64LE(src.gp(), dst_op, r0);
} else {
StoreU64(src.gp(), dst_op, r0);
}
break;
case StoreType::kF32Store:
if (is_store_mem) {
Register scratch2 = GetUnusedRegister(kGpReg, pinned).gp();
StoreF32LE(src.fp(), dst_op, r0, scratch2);
} else {
StoreF32(src.fp(), dst_op, r0);
}
break;
case StoreType::kF64Store:
if (is_store_mem) {
Register scratch2 = GetUnusedRegister(kGpReg, pinned).gp();
StoreF64LE(src.fp(), dst_op, r0, scratch2);
} else {
StoreF64(src.fp(), dst_op, r0);
}
break;
case StoreType::kS128Store: {
bailout(kUnsupportedArchitecture, "SIMD");
break;
}
default:
UNREACHABLE();
}
}
void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr,
Register offset_reg, uintptr_t offset_imm,
LoadType type, LiftoffRegList pinned) {
Load(dst, src_addr, offset_reg, offset_imm, type, pinned, nullptr, true);
lwsync();
}
void LiftoffAssembler::AtomicStore(Register dst_addr, Register offset_reg,
uintptr_t offset_imm, LiftoffRegister src,
StoreType type, LiftoffRegList pinned) {
lwsync();
Store(dst_addr, offset_reg, offset_imm, src, type, pinned, nullptr, true);
sync();
}
#ifdef V8_TARGET_BIG_ENDIAN
constexpr bool is_be = true;
#else
constexpr bool is_be = false;
#endif
#define ATOMIC_OP(instr) \
{ \
Register offset = r0; \
if (offset_imm != 0) { \
mov(ip, Operand(offset_imm)); \
if (offset_reg != no_reg) { \
add(ip, ip, offset_reg); \
} \
offset = ip; \
} else { \
if (offset_reg != no_reg) { \
offset = offset_reg; \
} \
} \
\
MemOperand dst = MemOperand(offset, dst_addr); \
\
switch (type.value()) { \
case StoreType::kI32Store8: \
case StoreType::kI64Store8: { \
auto op_func = [&](Register dst, Register lhs, Register rhs) { \
instr(dst, lhs, rhs); \
}; \
AtomicOps<uint8_t>(dst, value.gp(), result.gp(), r0, op_func); \
break; \
} \
case StoreType::kI32Store16: \
case StoreType::kI64Store16: { \
auto op_func = [&](Register dst, Register lhs, Register rhs) { \
if (is_be) { \
Register scratch = GetRegisterThatIsNotOneOf(lhs, rhs, dst); \
push(scratch); \
ByteReverseU16(dst, lhs, scratch); \
instr(dst, dst, rhs); \
ByteReverseU16(dst, dst, scratch); \
pop(scratch); \
} else { \
instr(dst, lhs, rhs); \
} \
}; \
AtomicOps<uint16_t>(dst, value.gp(), result.gp(), r0, op_func); \
if (is_be) { \
ByteReverseU16(result.gp(), result.gp(), ip); \
} \
break; \
} \
case StoreType::kI32Store: \
case StoreType::kI64Store32: { \
auto op_func = [&](Register dst, Register lhs, Register rhs) { \
if (is_be) { \
Register scratch = GetRegisterThatIsNotOneOf(lhs, rhs, dst); \
push(scratch); \
ByteReverseU32(dst, lhs, scratch); \
instr(dst, dst, rhs); \
ByteReverseU32(dst, dst, scratch); \
pop(scratch); \
} else { \
instr(dst, lhs, rhs); \
} \
}; \
AtomicOps<uint32_t>(dst, value.gp(), result.gp(), r0, op_func); \
if (is_be) { \
ByteReverseU32(result.gp(), result.gp(), ip); \
} \
break; \
} \
case StoreType::kI64Store: { \
auto op_func = [&](Register dst, Register lhs, Register rhs) { \
if (is_be) { \
ByteReverseU64(dst, lhs); \
instr(dst, dst, rhs); \
ByteReverseU64(dst, dst); \
} else { \
instr(dst, lhs, rhs); \
} \
}; \
AtomicOps<uint64_t>(dst, value.gp(), result.gp(), r0, op_func); \
if (is_be) { \
ByteReverseU64(result.gp(), result.gp()); \
} \
break; \
} \
default: \
UNREACHABLE(); \
} \
}
void LiftoffAssembler::AtomicAdd(Register dst_addr, Register offset_reg,
uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type) {
ATOMIC_OP(add);
}
void LiftoffAssembler::AtomicSub(Register dst_addr, Register offset_reg,
uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type) {
ATOMIC_OP(sub);
}
void LiftoffAssembler::AtomicAnd(Register dst_addr, Register offset_reg,
uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type) {
ATOMIC_OP(and_);
}
void LiftoffAssembler::AtomicOr(Register dst_addr, Register offset_reg,
uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type) {
ATOMIC_OP(orx);
}
void LiftoffAssembler::AtomicXor(Register dst_addr, Register offset_reg,
uintptr_t offset_imm, LiftoffRegister value,
LiftoffRegister result, StoreType type) {
ATOMIC_OP(xor_);
}
void LiftoffAssembler::AtomicExchange(Register dst_addr, Register offset_reg,
uintptr_t offset_imm,
LiftoffRegister value,
LiftoffRegister result, StoreType type) {
Register offset = r0;
if (offset_imm != 0) {
mov(ip, Operand(offset_imm));
if (offset_reg != no_reg) {
add(ip, ip, offset_reg);
}
offset = ip;
} else {
if (offset_reg != no_reg) {
offset = offset_reg;
}
}
MemOperand dst = MemOperand(offset, dst_addr);
switch (type.value()) {
case StoreType::kI32Store8:
case StoreType::kI64Store8: {
TurboAssembler::AtomicExchange<uint8_t>(dst, value.gp(), result.gp());
break;
}
case StoreType::kI32Store16:
case StoreType::kI64Store16: {
if (is_be) {
Register scratch = GetRegisterThatIsNotOneOf(value.gp(), result.gp());
push(scratch);
ByteReverseU16(r0, value.gp(), scratch);
pop(scratch);
TurboAssembler::AtomicExchange<uint16_t>(dst, r0, result.gp());
ByteReverseU16(result.gp(), result.gp(), ip);
} else {
TurboAssembler::AtomicExchange<uint16_t>(dst, value.gp(), result.gp());
}
break;
}
case StoreType::kI32Store:
case StoreType::kI64Store32: {
if (is_be) {
Register scratch = GetRegisterThatIsNotOneOf(value.gp(), result.gp());
push(scratch);
ByteReverseU32(r0, value.gp(), scratch);
pop(scratch);
TurboAssembler::AtomicExchange<uint32_t>(dst, r0, result.gp());
ByteReverseU32(result.gp(), result.gp(), ip);
} else {
TurboAssembler::AtomicExchange<uint32_t>(dst, value.gp(), result.gp());
}
break;
}
case StoreType::kI64Store: {
if (is_be) {
ByteReverseU64(r0, value.gp());
TurboAssembler::AtomicExchange<uint64_t>(dst, r0, result.gp());
ByteReverseU64(result.gp(), result.gp());
} else {
TurboAssembler::AtomicExchange<uint64_t>(dst, value.gp(), result.gp());
}
break;
}
default:
UNREACHABLE();
}
}
void LiftoffAssembler::AtomicCompareExchange(
Register dst_addr, Register offset_reg, uintptr_t offset_imm,
LiftoffRegister expected, LiftoffRegister new_value, LiftoffRegister result,
StoreType type) {
Register offset = r0;
if (offset_imm != 0) {
mov(ip, Operand(offset_imm));
if (offset_reg != no_reg) {
add(ip, ip, offset_reg);
}
offset = ip;
} else {
if (offset_reg != no_reg) {
offset = offset_reg;
}
}
MemOperand dst = MemOperand(offset, dst_addr);
switch (type.value()) {
case StoreType::kI32Store8:
case StoreType::kI64Store8: {
TurboAssembler::AtomicCompareExchange<uint8_t>(
dst, expected.gp(), new_value.gp(), result.gp(), r0);
break;
}
case StoreType::kI32Store16:
case StoreType::kI64Store16: {
if (is_be) {
Push(new_value.gp(), expected.gp());
Register scratch = GetRegisterThatIsNotOneOf(
new_value.gp(), expected.gp(), result.gp());
push(scratch);
ByteReverseU16(new_value.gp(), new_value.gp(), scratch);
ByteReverseU16(expected.gp(), expected.gp(), scratch);
pop(scratch);
TurboAssembler::AtomicCompareExchange<uint16_t>(
dst, expected.gp(), new_value.gp(), result.gp(), r0);
ByteReverseU16(result.gp(), result.gp(), r0);
Pop(new_value.gp(), expected.gp());
} else {
TurboAssembler::AtomicCompareExchange<uint16_t>(
dst, expected.gp(), new_value.gp(), result.gp(), r0);
}
break;
}
case StoreType::kI32Store:
case StoreType::kI64Store32: {
if (is_be) {
Push(new_value.gp(), expected.gp());
Register scratch = GetRegisterThatIsNotOneOf(
new_value.gp(), expected.gp(), result.gp());
push(scratch);
ByteReverseU32(new_value.gp(), new_value.gp(), scratch);
ByteReverseU32(expected.gp(), expected.gp(), scratch);
pop(scratch);
TurboAssembler::AtomicCompareExchange<uint32_t>(
dst, expected.gp(), new_value.gp(), result.gp(), r0);
ByteReverseU32(result.gp(), result.gp(), r0);
Pop(new_value.gp(), expected.gp());
} else {
TurboAssembler::AtomicCompareExchange<uint32_t>(
dst, expected.gp(), new_value.gp(), result.gp(), r0);
}
break;
}
case StoreType::kI64Store: {
if (is_be) {
Push(new_value.gp(), expected.gp());
ByteReverseU64(new_value.gp(), new_value.gp());
ByteReverseU64(expected.gp(), expected.gp());
TurboAssembler::AtomicCompareExchange<uint64_t>(
dst, expected.gp(), new_value.gp(), result.gp(), r0);
ByteReverseU64(result.gp(), result.gp());
Pop(new_value.gp(), expected.gp());
} else {
TurboAssembler::AtomicCompareExchange<uint64_t>(
dst, expected.gp(), new_value.gp(), result.gp(), r0);
}
break;
}
default:
UNREACHABLE();
}
}
void LiftoffAssembler::AtomicFence() { sync(); }
void LiftoffAssembler::LoadCallerFrameSlot(LiftoffRegister dst,
uint32_t caller_slot_idx,
ValueKind kind) {
int32_t offset = (caller_slot_idx + 1) * kSystemPointerSize;
switch (kind) {
case kI32: {
#if defined(V8_TARGET_BIG_ENDIAN)
LoadS32(dst.gp(), MemOperand(fp, offset + 4), r0);
break;
#else
LoadS32(dst.gp(), MemOperand(fp, offset), r0);
break;
#endif
}
case kRef:
case kRtt:
case kOptRef:
case kI64: {
LoadU64(dst.gp(), MemOperand(fp, offset), r0);
break;
}
case kF32: {
LoadF32(dst.fp(), MemOperand(fp, offset), r0);
break;
}
case kF64: {
LoadF64(dst.fp(), MemOperand(fp, offset), r0);
break;
}
case kS128: {
bailout(kSimd, "simd load");
break;
}
default:
UNREACHABLE();
}
}
void LiftoffAssembler::StoreCallerFrameSlot(LiftoffRegister src,
uint32_t caller_slot_idx,
ValueKind kind) {
int32_t offset = (caller_slot_idx + 1) * kSystemPointerSize;
switch (kind) {
case kI32: {
#if defined(V8_TARGET_BIG_ENDIAN)
StoreU32(src.gp(), MemOperand(fp, offset + 4), r0);
break;
#else
StoreU32(src.gp(), MemOperand(fp, offset), r0);
break;
#endif
}
case kRef:
case kRtt:
case kOptRef:
case kI64: {
StoreU64(src.gp(), MemOperand(fp, offset), r0);
break;
}
case kF32: {
StoreF32(src.fp(), MemOperand(fp, offset), r0);
break;
}
case kF64: {
StoreF64(src.fp(), MemOperand(fp, offset), r0);
break;
}
case kS128: {
bailout(kSimd, "simd load");
break;
}
default:
UNREACHABLE();
}
}
void LiftoffAssembler::LoadReturnStackSlot(LiftoffRegister dst, int offset,
ValueKind kind) {
switch (kind) {
case kI32: {
#if defined(V8_TARGET_BIG_ENDIAN)
LoadS32(dst.gp(), MemOperand(sp, offset + 4), r0);
break;
#else
LoadS32(dst.gp(), MemOperand(sp, offset), r0);
break;
#endif
}
case kRef:
case kRtt:
case kOptRef:
case kI64: {
LoadU64(dst.gp(), MemOperand(sp, offset), r0);
break;
}
case kF32: {
LoadF32(dst.fp(), MemOperand(sp, offset), r0);
break;
}
case kF64: {
LoadF64(dst.fp(), MemOperand(sp, offset), r0);
break;
}
case kS128: {
bailout(kSimd, "simd load");
break;
}
default:
UNREACHABLE();
}
}
#ifdef V8_TARGET_BIG_ENDIAN
constexpr int stack_bias = -4;
#else
constexpr int stack_bias = 0;
#endif
void LiftoffAssembler::MoveStackValue(uint32_t dst_offset, uint32_t src_offset,
ValueKind kind) {
DCHECK_NE(dst_offset, src_offset);
switch (kind) {
case kI32:
case kF32:
LoadU32(ip, liftoff::GetStackSlot(src_offset + stack_bias), r0);
StoreU32(ip, liftoff::GetStackSlot(dst_offset + stack_bias), r0);
break;
case kI64:
case kOptRef:
case kRef:
case kRtt:
case kF64:
LoadU64(ip, liftoff::GetStackSlot(src_offset), r0);
StoreU64(ip, liftoff::GetStackSlot(dst_offset), r0);
break;
case kS128:
bailout(kSimd, "simd op");
break;
default:
UNREACHABLE();
}
}
void LiftoffAssembler::Move(Register dst, Register src, ValueKind kind) {
mr(dst, src);
}
void LiftoffAssembler::Move(DoubleRegister dst, DoubleRegister src,
ValueKind kind) {
if (kind == kF32 || kind == kF64) {
fmr(dst, src);
} else {
bailout(kSimd, "simd op");
}
}
void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueKind kind) {
DCHECK_LT(0, offset);
RecordUsedSpillOffset(offset);
switch (kind) {
case kI32:
StoreU32(reg.gp(), liftoff::GetStackSlot(offset + stack_bias), r0);
break;
case kI64:
case kOptRef:
case kRef:
case kRtt:
StoreU64(reg.gp(), liftoff::GetStackSlot(offset), r0);
break;
case kF32:
StoreF32(reg.fp(), liftoff::GetStackSlot(offset + stack_bias), r0);
break;
case kF64:
StoreF64(reg.fp(), liftoff::GetStackSlot(offset), r0);
break;
case kS128: {
bailout(kSimd, "simd op");
break;
}
default:
UNREACHABLE();
}
}
void LiftoffAssembler::Spill(int offset, WasmValue value) {
RecordUsedSpillOffset(offset);
UseScratchRegisterScope temps(this);
Register src = no_reg;
src = ip;
switch (value.type().kind()) {
case kI32: {
mov(src, Operand(value.to_i32()));
StoreU32(src, liftoff::GetStackSlot(offset + stack_bias), r0);
break;
}
case kI64: {
mov(src, Operand(value.to_i64()));
StoreU64(src, liftoff::GetStackSlot(offset), r0);
break;
}
default:
// We do not track f32 and f64 constants, hence they are unreachable.