how to read v register if vslide1down instruction not present

[fanghuaqi]

Hi, I am wondering if a risc-v vector don't have vslide1down instruction, how to read the vector register

riscv-openocd/src/target/riscv/riscv-013.c

Lines 2522 to 2546 in ae7ffa4

	for (unsigned int i = 0; i < debug_vl; i++) {
	/* Can't reuse the same program because riscv_program_exec() adds
	* ebreak to the end every time. */
	struct riscv_program program;
	riscv_program_init(&program, target);
	riscv_program_insert(&program, vmv_x_s(S0, vnum));
	riscv_program_insert(&program, vslide1down_vx(vnum, vnum, S0, true));
	/* Executing the program might result in an exception if there is some
	* issue with the vector implementation/instructions we're using. If that
	* happens, attempt to restore as usual. We may have clobbered the
	* vector register we tried to read already.
	* For other failures, we just return error because things are probably
	* so messed up that attempting to restore isn't going to help. */
	result = riscv_program_exec(&program, target);
	if (result == ERROR_OK) {
	riscv_reg_t v;
	if (register_read_direct(target, &v, GDB_REGNO_S0) != ERROR_OK)
	return ERROR_FAIL;
	buf_set_u64(value, debug_vsew * i, debug_vsew, v);
	} else {
	LOG_TARGET_ERROR(target,
	"Failed to execute vmv/vslide1down while reading %s",
	gdb_regno_name(target, regno));
	break;

Is there any other way to read vector register in openocd?

Thanks

[TommyMurphyTM1234]

I find the way that specifications are published very confusing.

If I go here:

• https://riscv.org/technical/specifications/

It says:

ISA Specifications (Ratified)

The specifications shown below represent the current, ratified and published releases.

• Volume 1, Unprivileged Specification version 20240411 [PDF][GitHub]

But if I download that PDF then it says:

31.1. Introduction

This document is version 1.1-draft of the RISC-V vector extension.

Which contradicts the earlier comment that the docs linked are "the current, ratified and published releases".

I'm trying to see what version of the RISC-V V vector extension the "vector slide" instructions belong to but I can't seem to ascertain that.

Edit: I logged and issue here:

• RISC-V Specifications page is confusing/incorrect? riscv/riscv-isa-manual#1400

[fanghuaqi]

vslide1down list as below

[TommyMurphyTM1234]

vslide1down list as below

Yes - but that doesn't clarify what version of the V extension spec that it's part of and if OpenOCD has some implicit dependency on a specific version of the extension spec.

[aap-sc]

@fanghuaqi regardless of the version of the spec. Current implementation assumes that vslide1down is present. If this instruction is not support by your target - you won't be able to read vector registers. Patches or issues are welcome.

[TommyMurphyTM1234]

What is the nature of the RISC-V target that you're using that does not support vslide1down?
In particular what version of the RISC-V V vector extension does it implement?

[fanghuaqi]

@fanghuaqi regardless of the version of the spec. Current implementation assumes that vslide1down is present. If this instruction is not support by your target - you won't be able to read vector registers. Patches or issues are welcome.

Hi @aap-sc , is there any other way to implement read vector register in openocd

[TommyMurphyTM1234]

Is this of any relevance here perhaps?

• Update to version 1.0 of the vector spec. #505

Accessing registers on targets that implement 0.9 or earlier will no
longer work.

If not then it might be worth reviewing other PRs related to vector register accesses - i.e. some or all of the following:

• https://github.com/riscv-collab/riscv-openocd/pulls?q=is%3Apr+vector+registers

[aap-sc]

What is the nature of the RISC-V target that you're using that does not support vslide1down?

@fanghuaqi there may be many ways. The recommended way for external debugger is to use vslide1down. If vslide1down is not supported one could try to write the values to memory using vector stores. This will require user to configure "working area", though this will somewhat complicate the implementation.

Unless the official specification allows for the targets without vslide1down instruction I will strongly object against merging such implementation since it will be hard to maintain. Still, you can always implement the required support in your fork, or point out if such implementation is indeed allowed by the spec.

[fanghuaqi]

Hi @aap-sc , thanks for your explaination, I will see how to implement it using the way you suggest.

[TommyMurphyTM1234]

Unless the official specification allows for the targets without vslide1down instruction I will strongly object against merging such implementation

But that's my confusion here - what official specification (and version)? I presume you mean a ratified version of the V vector extension? But what version? Isn't 1.0 the only ratified version so far? Does it include vslide1down? I can't seem to find an authoritative V extension 1.0 spec and the unprivileged ISA spec linked from the RISC-V International page is supposed to be ratified but still contains draft extension narrative. Very confusing... :-|

[aap-sc]

But that's my confusion here - what official specification (and version)?

https://github.com/riscv/riscv-v-spec/releases/download/v1.0/riscv-v-spec-1.0.pdf (1.0, not ratified, FROZEN, public review)
https://github.com/riscv/riscv-v-spec/releases/download/zvfh/zvfh-public-review-complete.pdf (1.1, not ratified, FROZEN, public review COMPLETE)

I presume you mean a ratified version of the V vector extension? But what version? Isn't 1.0 the only ratified version so far?

There is no ratified version currently. HOWEVER, the versions presented above are FROZEN. This means that no major changes are expected before the formal ratification.

I can't seem to find an authoritative V extension 1.0 spec and the unprivileged ISA spec linked from the RISC-V International page is supposed to be ratified but still contains draft extension narrative.

I've provided the links above. While these are marked as "draft" - these are frozen. Vector Slidedown/Slideup Instructions seems to be mandatory in these specifications.

[TommyMurphyTM1234]

There is no ratified version currently. HOWEVER, the versions presented above are FROZEN. This means that no major changes are expected before the formal ratification.

As I said - it's confusing...

• https://wiki.riscv.org/display/HOME/Ratified+Extensions

[aap-sc]

As I said - it's confusing...

O_o. Yeah... Quite unexpected.

[TommyMurphyTM1234]

As I said - it's confusing...

O_o. Yeah... Quite unexpected.

Yes - and also strange that the vector extension ostensibly ratified in 2021 was only officially announced this year:

• https://riscv.org/announcements/2024/04/risc-v-international-achieves-milestone-with-ratification-of-40-specifications-in-two-years/

[aap-sc]

@TommyMurphyTM1234 , however. If we look here:

https://riscv.org/technical/specifications/ , there is this document "Volume 1, Unprivileged Specification version 20240411 " which seems to be ratified. Vector isa is present there.
https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view?usp=drive_link

[TommyMurphyTM1234]

https://riscv.org/technical/specifications/ , there is this document "Volume 1, Unprivileged Specification version 20240411 " which seems to be ratified.

That page says that it's ratified but it still contains draft info.
That's what I was saying earlier above:

• how to read v register if vslide1down instruction not present #1069 (comment)

and here:

• RISC-V Specifications page is confusing/incorrect? riscv/riscv-isa-manual#1400

[aap-sc]

@TommyMurphyTM1234 yeah. riscv/riscv-isa-manual#1400 - this good thing we have this issue. I hope that the situation will be clarified soon.

[aap-sc]

@fanghuaqi could you please clarify if your question is answered? If you have plans to submit MR we can leave this issue open (it would not hurt to rename then), otherwise I suggest to close the issue.

[fanghuaqi]

Yes, you can close it, we implement read csr not using vslidedown instruction, but require working memory.

Thanks