{"payload":{"header_redesign_enabled":false,"results":[{"id":"318646529","archived":false,"color":"#b2b7f8","followers":4,"has_funding_file":false,"hl_name":"rlee287/hardware-bus-infrastructure","hl_trunc_description":"A collection of formal properties for hardware buses, and cores using them.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":318646529,"name":"hardware-bus-infrastructure","owner_id":14067959,"owner_login":"rlee287","updated_at":"2021-02-22T05:47:39.229Z","has_issues":true}},"sponsorable":false,"topics":["psl","sva","wishbone-bus","axi4","axi4-lite","axi4-stream","bus-standards"],"type":"Public","help_wanted_issues_count":1,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":57,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Arlee287%252Fhardware-bus-infrastructure%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/rlee287/hardware-bus-infrastructure/star":{"post":"TBhz84nVHqvhdKclYXMbt9wYOw2XqLqQ1X0lYi9HWQ0QwAZ4LMi-mSTGyju0hwZgtHUsp8uD3eEXL-WO4RaJhQ"},"/rlee287/hardware-bus-infrastructure/unstar":{"post":"51BB0t03-UGIsO5wg6TV-3wv6kWjNnFb_fm8CWk7B58Q9tJN0K0AWrye4oj-FDK8wrnKAsrTYkUqCA7T3cd-0w"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"ki7amZnwqRpnudAnjNj9yn7ibbzZpkTxVEMqqBOSXpNQ7EGutsVBwtERJKrO8TO-v1IpB5BSXqa_GlBYpx00Sw"}}},"title":"Repository search results"}