RISC-V support

[luser]

I glanced at the breakpad-dev mailing list and noticed that in September, support for RISC-V minidumps from Linux was merged.

At a minimum, adding the RISC-V CPU context values would be useful, so that RISC-V minidumps don't show up as an unknown CPU, and we don't accidentally allocate conflicting values:
https://github.com/google/breakpad/blob/837b0f5d52701df4a88b94eaa8b0a093e33ff45d/src/google_breakpad/common/minidump_format.h#L687-L688

The next step from that would be to add matching CPU context structs for RISC-V 32/64, so CPU contexts could be parsed and displayed:
https://github.com/google/breakpad/blob/837b0f5d52701df4a88b94eaa8b0a093e33ff45d/src/google_breakpad/common/minidump_cpu_riscv.h

Porting the stackwalker implementations for RISC-V 32/64 should provide full parity with the breakpad implementation. That'd be a much larger chunk of work, and unless someone using these crates needs it it doesn't seem terribly important, but it could be a fun exercise for someone to practice writing Rust:
https://github.com/google/breakpad/blob/28cf16bc342c0e39f867ccc1a30357a803b9a15a/src/processor/stackwalker_riscv.cc
https://github.com/google/breakpad/blob/837b0f5d52701df4a88b94eaa8b0a093e33ff45d/src/processor/stackwalker_riscv64.cc

There are unit tests for the stackwalker implementations that could be ported alongside to verify correctness:
https://github.com/google/breakpad/blob/28cf16bc342c0e39f867ccc1a30357a803b9a15a/src/processor/stackwalker_riscv_unittest.cc
https://github.com/google/breakpad/blob/28cf16bc342c0e39f867ccc1a30357a803b9a15a/src/processor/stackwalker_riscv64_unittest.cc