AXI Interconnect problems

[a60626316]

Hi,

I would like to try adding an axi_interconnect module between the SCR1 and memory for simulation. Additionally, if possible, I would also like to add some simple slaves to the axi to form a basic SoC.
Originally, in scr1_top_tb_axi, the SCR1 and memory were directly connected. However, I encountered some difficulties when trying to add an axi_interconnect module between SCR1 and memory. I modified scr1_top_tb_axi and added the axi module. The command I am using is: make run_vcs CFG=CUSTOM BUS=AXI ARCH=I VECT_IRQ=0 IPIC=0 TCM=0 TARGETS="hello". When I set the BASE_ADDR to 0x200 (the starting address of SCR1), an 'not aligned' error occurs.

Furthermore, I noticed descriptions related to 'addr' in the scr1_imem_router.sv and scr1_dmem_router.sv files. Therefore, setting the BASE_ADDR to 0x10000 and BASE_ADDR to 0x480000 (which are connected to this parameter in scr1_top_axi) also did not work properly.

I would like to ask for advice on how to correctly set the memory address. Thank you very much for your help!

Additional information: The axi interconnect module I am using is from the following URL:
https://github.com/alexforencich/verilog-axi
If you have any recommendations on which module to use, please let me know. Thank you so much.

Best regards,
Jui

[a60626316]

I tried another method where the SCR1 and the memory's IMEM interface are directly connected, while the DMEM interfaces are all connected to the axi, as shown in the diagram below:

Additionally, I set the BASE_ADDR of the axi to 0. This allows the simulation to proceed smoothly. However, When I observe the waveform, I noticed that the instructions stop midway through execution. I'm not sure if there are additional settings that need to be configured?
orignal

modified

[achuykov-sc]

Hi @a60626316,

Could you please clarify a few things?

1. Could you confirm that CPU should not stop at that moment? For example, the WFI instruction halts the core
2. We have a timeout in default testbench. Please check that is not your case.

In any case, I'm proposing to check addresses and data on AXI to avoid reading wrong addresses or decode invalid instruction.

BR,
Alexander

[a60626316]

Hi, @achuykov-sc ,
Regarding the issue I mentioned in my second message, the stoppage was not due to a Timeout, but rather occurred while writing data to memory. However, after I reassembled each module and adjusted the parameters, it is now functioning normally, thank you.
Additionally, although I can currently operate using the second method, I would still like to inquire about the feasibility of using the first method of connection. If it is feasible, how should the AXI address be set? Thank you for your reply.

Best regards,
Jui