AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
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Updated
May 29, 2024 - VHDL
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
A collection of formal properties for hardware buses, and cores using them.
HLS for Networks-on-Chip
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
AXI4 and AXI4-Lite interface definitions
OLED driver demo running on ZedBoard
A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
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