Click Bait Filter Backend (Prototype_Server)

A presentation about Advanced Microcontroller Bus Architecture

Verilog header for easier AXI interface declaration & connection

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Synchronous and Asynchronous FIFO with AXI interface

just some files that show one simple way to simulate some axi cycles.

Statistics Acquisition Module on Verilog

Build an open source, extremely simple DMA.

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

Сервис по подбору доступного жилья.

PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx

FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.

Learning Resources for AXI made by self

Spotify Clone With Reactjs

Set of useful tools around the Axie infinity game.

RSS Aggregator is a web application that collects, parses, and displays news feeds from various sources, offering a multi-language, user-friendly interface for managing and reading RSS feeds.

Custom AXI GPIO core with up to 32 input and 32 output ports

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.