axi
Here are 67 public repositories matching this topic...
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Oct 7, 2023 - TypeScript
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
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Apr 13, 2024 - VHDL
Spotify Clone With Reactjs
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Jan 2, 2022 - JavaScript
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Sep 16, 2023 - JavaScript
A comprehensive MERN stack project for online learning, connecting students with teachers, enabling class management, assignments, and seamless admin oversight.
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Jan 7, 2024 - JavaScript
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
FPGA interface and driver for an OV7670 camera sensor.
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Aug 28, 2023 - VHDL
Реализация AXI интерфейса на SystemVerilog
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Mar 6, 2024 - SystemVerilog
Сервис по подбору доступного жилья.
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Sep 16, 2023 - JavaScript
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
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May 1, 2020 - Tcl
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