axi
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just some files that show one simple way to simulate some axi cycles.
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May 27, 2016 - Verilog
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
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Mar 24, 2017 - VHDL
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Jun 5, 2017 - SystemVerilog
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
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Jul 12, 2017 - VHDL
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
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Nov 21, 2017 - Verilog
ASIC for executing vectorized gradient descent on linear regression problems.
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Aug 13, 2018 - VHDL
Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
Hardware and Software Co-design implementations
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Dec 5, 2019
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
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May 1, 2020 - Tcl
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
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May 1, 2020 - Tcl
OPAE porting to Xilinx FPGA devices.
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Aug 5, 2020 - Coq
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