Code collective of my 3rd Semester at ITER
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Updated
Jan 20, 2024 - HTML
Code collective of my 3rd Semester at ITER
implementation of a machine executes simple operations in general built-in registers in Verilog
This repository contains all the stuff that I have learned at MERL-UIT during the training session. This is available for everyone so you can check that out for learning stuff as well.
Course Project for EE224 (Digital Systems) offered in Autumn 2023
This Project is about 7 segment display of an ID using Different Gates and Multiplexers,Decoders
Final examination of Digital Logic Design course (Reti Logiche) - A.Y. 2018/2019 Politecnico di Milano
Course website for ECE275: Sequential logic systems, Fall 2021 for the University of Maine
Microprocessor design with Quartus by using Verilog Programming.
This is a test project to implement digital logic design using Logic Works 4
A Digital Logic Design based project working the implementation of Stack Data Structure using all the gates including AND,OR,XOR,XNOR and MUX.Works on LogicWorks 5
Digital Logic Design (.circ) related files can be found here. You must run those files in Logisim software.
Simple design of interconnected state machines.
Xilinx Vivado project for nanoprocessor designing with VHDL
converts a stg (.g file generated by workcraft) to a verilogA model
This repository contains all the academic projects made during the studies for the Bachelor's Degree in Engineering of Computing Systems and for the M.Sc. in Data Science.
This is simple design of finite state machines in Digital Logic Design using VHDL.
8x8 LED Matrix built using MAX7219 modules and arduino.
Karnaugh maps solver is a web app that takes the truth table of a function as input, transposes it onto the respective Karnaugh map and finds the minimum forms SOP and POS according to the visual resolution method by Maurice Karnaugh, American physicist and mathematician. Implementation of the Quine - McKlusky algorithm in C++
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