Test DRAM for bit flips caused by the rowhammer problem

Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs

This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following paper: Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms", SIGMETRICS 2017. https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf

A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips

Demo: https://mohin7.github.io/dramkit1/

Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.

Tester for DRAM modules

**No Longer Maintained** Official RAMCloud repo

A 1MB chip RAM expansion for the A500+

A High-Level DRAM Timing, Power and Area Exploration Tool

Repo for my master thesis

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.

Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omu…

BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.

DRAMSim2: A cycle accurate DRAM simulator

Commodore C386SX-LT 2MB memory module schematics

A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput

MIPS ISA simulator which implements non-blocking DRAM access

MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution