An implementation of mips architecture on FPGA using verilog
-
Updated
Jul 31, 2021 - Verilog
An implementation of mips architecture on FPGA using verilog
Yahtzee game designed in VHDL for Digital System Design Course in EPFL BA2 (IC Section) Grade: 88.89%
A compilation of several different coding challenges/exercises/drillings that I did when in my junior year. The very reason of this repo is nostalgia/documenting my first lines of code(non-projects). I might add more when seen fit.
A hardware description and simulation language that allows users to simulate the behavior of a hardware system in a easy, intuitive and fast way.
Implementing a 4-bit Kogge Stone Adder (a type of carry-tree adder) in VHDL using XIlinx Vivado
Communication of a CPLD with the analog-to-digital converter ADC0832 (modeled in VHDL)
B.Tech CSE @ NITC
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
Computer Architecture Project
Simple Central Processing Unit (CPU) Design using Terasic DE-10 Standard FPGA
This is digital design project written in Verilog.
Projeto Final da Disciplina de Circuitos Lógicos II em Verilog usando a IDE do Quartus II
Building a modern computer from first principles. (Projects from the nand2Tetris computer systems course)
Course Project for EE224 (Digital Systems) offered in Autumn 2023
5 stage pipelined risc processor written in SystemC
Basic Stopwatch Design using Terasic DE-10 Standard FPGA
my work at Coursera's Nand2Tetris part1 course
In this project-centered course I built a modern computer system (The Hack Computer), from the ground up.
This implements a simple median filter on hardware.
Add a description, image, and links to the hardware-description-language topic page so that developers can more easily learn about it.
To associate your repository with the hardware-description-language topic, visit your repo's landing page and select "manage topics."