high instruction-level-parallelism (ILP) using Resource-Flow-Execution
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Updated
May 26, 2024 - C
high instruction-level-parallelism (ILP) using Resource-Flow-Execution
Náčrtky a bloková schémata pro (mikro)procesory do předmětu HAW a nejen
Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.
This repository contains an HPC (High Performance Computing) reliability benchmark, carrying out fault injection experiments on a variety of HPC applications, targeting BLAS (Basic Linear Algebra Subroutines) GEMM (GEneral Matrix Multiply) operations.
RISCV processor done in both single cycle and pipeline (with CSR support) form.
Sumador de dos números de dos dígitos cada uno codificados en ASCII estándar en 7 bits. Restricción: realizar la suma en binario natural.
Some utility programs I created to help simplify my life wrt hw development tool usage
Hardware Description (and Simulation) Library
unipolar dummy load testing utility
Project for Computer Design course.
Hardware-Scheduled Pipeline Processor in VHDL
Working-zone encoding: Digital Devices Project, Final Examination 2019/2020 - Politecnico di Milano
This project was a nice idea I had to build a digital logic clock on the DE1-SOC FPGA, while practicing System-verilog, Asynchronous design, and advanced debugging techniques
Projeto de relógio digital com projeto de arquitetura, assembler e assembly. Feito como Projeto 1 da disciplina Design de Computadores, do 6° semestre de Engenharia da Computação do Insper.
KiCad project and OpenSCAD model for a custom NeoPixel ring which uses a USB-C socket to interface with LEDswarm controller mainboards.
Instruction Set Architecture and pipeline to implement a new operation in the computer hardware.
Robust SystemVerilog Linter and Formatter to enhance code quality and ensure standards compliance. Perfect for hardware designers seeking efficient verification and readable code.
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