🚦 A digital controller to control traffic in Verilog HDL
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Updated
Aug 12, 2019 - Verilog
🚦 A digital controller to control traffic in Verilog HDL
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
Beginner-level university work on low-level programming and understanding of digital computing components.
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A Repo that contains the source code for Digital Design and Computer Organisation course.
16 bit IEEE floating point implementation or the UK PinKY pipelined processsor architecture.
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chip8 verilog implementation targeting the terasic de0-nano dev kit
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