An abstraction library for interfacing EDA tools
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Updated
May 17, 2024 - Python
An abstraction library for interfacing EDA tools
HDL support for VS Code
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
SHA256 in (System-) Verilog / Open Source FPGA Miner
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
XCrypto: a cryptographic ISE for RISC-V
Quickstart guide on Icarus Verilog.
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
🌱 Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
💎 A 32-bit ARM Processor Implementation in Verilog HDL
Just a set of Dockerfiles and tools for FuseSoC
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
Guides on how to install a SystemVerilog toolchain on different operating systems
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
🚦 A digital controller to control traffic in Verilog HDL
A Repo that contains the source code for Digital Design and Computer Organisation course.
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