A real time computing machine
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Updated
Apr 12, 2017 - C
A real time computing machine
One Instruction Set Computer
An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".
A real time computing machine
Register file cache implementation on the Marssx86 architectural simulator
A pedagogical processor on FPGA, developed at NIIT University.
[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor
Repository for the course MO601 - Computer Architecture II
some tlb experimentation code: calculate L1, L2 miss penalties and show cross-HT interference.
FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64
A small RISC-V core (SystemVerilog)
A small RISC-V core (VHDL)
an ARM9 compatible CPU core written in Verilog, and related experiments
Experiments with low level assembly language
Implements a BDP (Branch difference predictor) based on the paper by Timothy H Heil, Zak Smith and JE Smith - "Improving branch predictors by correlating on data values"
Presentation about software-based Micro-architectural Side-Channel attacks.
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
riscv_myth_workshop created by GitHub Classroom. Contains an implemented RISC-V 32-bit core.
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