Automate your SOC with SEKOIA.IO's Automation Library. Pull Requests are always welcome and highly appreciated!

Open source security data pipelines.

Security lists for SOC detections

Neural Turing Machine for a System on Chip verified with UVM/OSVVM/FV

System on Chip verified with UVM/OSVVM/FV

System on Chip with RISCV-32 / RISCV-64 / RISCV-128

System on Chip with OpenRISC-32 / OpenRISC-64

System on Chip with MSP430-16

Information Security, Risk mgmt. and Forensics.

Linux for ARM (LFA) - руководство по сборке из исходного кода системы, использующей ядро Linux, для компьютеров на архитектуре ARM. Данное руководство использует наработки проекта CLFS, а также ряд других источников, полный список которых приведён в списке литературы в самом руководстве.

MasterParser is a powerful DFIR tool designed for analyzing and parsing Linux logs

Purpleteam scripts simulation & Detection - trigger events for SOC detections

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

An AXI4 crossbar implementation in SystemVerilog

The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbs microcontroller

🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Userspace I/O library for Xilinx AXI S2MM DMA